Lines Matching refs:gpio_mmio_base
66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_i2c_reset()
67 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); in intel_i2c_reset()
193 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; in intel_gpio_setup()
213 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_hw_status()
250 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_wait_idle()
277 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_read_chunk()
332 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_write_chunk()
404 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_index_read()
449 reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer()
585 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA; in intel_setup_gmbus()
587 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; in intel_setup_gmbus()
589 dev_priv->gpio_mmio_base = 0; in intel_setup_gmbus()