Lines Matching refs:I915_WRITE
66 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0); in intel_i2c_reset()
67 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0); in intel_i2c_reset()
83 I915_WRITE(DSPCLK_GATE_D, val); in intel_i2c_quirk_set()
223 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en); in gmbus_wait_hw_status()
237 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_hw_status()
258 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN); in gmbus_wait_idle()
263 I915_WRITE(GMBUS4 + reg_offset, 0); in gmbus_wait_idle()
279 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_read_chunk()
342 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write_chunk()
343 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_write_chunk()
356 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write_chunk()
418 I915_WRITE(GMBUS5 + reg_offset, gmbus5); in gmbus_xfer_index_read()
424 I915_WRITE(GMBUS5 + reg_offset, 0); in gmbus_xfer_index_read()
452 I915_WRITE(GMBUS0 + reg_offset, bus->reg0); in gmbus_xfer()
482 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); in gmbus_xfer()
493 I915_WRITE(GMBUS0 + reg_offset, 0); in gmbus_xfer()
522 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); in gmbus_xfer()
523 I915_WRITE(GMBUS1 + reg_offset, 0); in gmbus_xfer()
524 I915_WRITE(GMBUS0 + reg_offset, 0); in gmbus_xfer()
547 I915_WRITE(GMBUS0 + reg_offset, 0); in gmbus_xfer()