191 	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);  in ibx_write_infoframe()
205 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in ibx_write_infoframe()
210 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);  in ibx_write_infoframe()
226 	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);  in ibx_infoframe_enabled()
240 	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);  in cpt_write_infoframe()
257 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in cpt_write_infoframe()
262 		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);  in cpt_write_infoframe()
278 	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);  in cpt_infoframe_enabled()
292 	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);  in vlv_write_infoframe()
306 		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);  in vlv_write_infoframe()
311 		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);  in vlv_write_infoframe()
327 	int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);  in vlv_infoframe_enabled()
544 	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);  in ibx_set_infoframes()
591 	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);  in cpt_set_infoframes()
629 	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);  in vlv_set_infoframes()
724 		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);  in intel_hdmi_prepare()
726 		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);  in intel_hdmi_prepare()
728 		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);  in intel_hdmi_prepare()
735 				    enum pipe *pipe)  in intel_hdmi_get_hw_state()  argument
753 		*pipe = PORT_TO_PIPE_CPT(tmp);  in intel_hdmi_get_hw_state()
755 		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);  in intel_hdmi_get_hw_state()
757 		*pipe = PORT_TO_PIPE(tmp);  in intel_hdmi_get_hw_state()
826 		enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);  in intel_enable_hdmi()
852 				 pipe_name(intel_crtc->pipe));  in intel_enable_hdmi()
879 		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;  in intel_disable_hdmi()  local
893 				intel_wait_for_vblank(dev, pipe);  in intel_disable_hdmi()
1287 	int pipe = intel_crtc->pipe;  in vlv_hdmi_pre_enable()  local
1292 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));  in vlv_hdmi_pre_enable()
1294 	if (pipe)  in vlv_hdmi_pre_enable()
1299 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);  in vlv_hdmi_pre_enable()
1302 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);  in vlv_hdmi_pre_enable()
1303 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);  in vlv_hdmi_pre_enable()
1304 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);  in vlv_hdmi_pre_enable()
1305 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);  in vlv_hdmi_pre_enable()
1306 	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);  in vlv_hdmi_pre_enable()
1307 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);  in vlv_hdmi_pre_enable()
1308 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);  in vlv_hdmi_pre_enable()
1309 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);  in vlv_hdmi_pre_enable()
1312 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);  in vlv_hdmi_pre_enable()
1313 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);  in vlv_hdmi_pre_enable()
1333 	int pipe = intel_crtc->pipe;  in vlv_hdmi_pre_pll_enable()  local
1339 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),  in vlv_hdmi_pre_pll_enable()
1342 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),  in vlv_hdmi_pre_pll_enable()
1349 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);  in vlv_hdmi_pre_pll_enable()
1350 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);  in vlv_hdmi_pre_pll_enable()
1351 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);  in vlv_hdmi_pre_pll_enable()
1353 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);  in vlv_hdmi_pre_pll_enable()
1354 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);  in vlv_hdmi_pre_pll_enable()
1366 	enum pipe pipe = intel_crtc->pipe;  in chv_hdmi_pre_pll_enable()  local
1374 	if (pipe != PIPE_B) {  in chv_hdmi_pre_pll_enable()
1375 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_hdmi_pre_pll_enable()
1381 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_hdmi_pre_pll_enable()
1383 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_hdmi_pre_pll_enable()
1389 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_hdmi_pre_pll_enable()
1393 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));  in chv_hdmi_pre_pll_enable()
1395 	if (pipe != PIPE_B)  in chv_hdmi_pre_pll_enable()
1399 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);  in chv_hdmi_pre_pll_enable()
1401 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));  in chv_hdmi_pre_pll_enable()
1403 	if (pipe != PIPE_B)  in chv_hdmi_pre_pll_enable()
1407 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);  in chv_hdmi_pre_pll_enable()
1414 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));  in chv_hdmi_pre_pll_enable()
1415 	if (pipe != PIPE_B)  in chv_hdmi_pre_pll_enable()
1419 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);  in chv_hdmi_pre_pll_enable()
1431 	int pipe = intel_crtc->pipe;  in vlv_hdmi_post_disable()  local
1435 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);  in vlv_hdmi_post_disable()
1436 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);  in vlv_hdmi_post_disable()
1448 	enum pipe pipe = intel_crtc->pipe;  in chv_hdmi_post_disable()  local
1454 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_hdmi_post_disable()
1456 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_hdmi_post_disable()
1458 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_hdmi_post_disable()
1460 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_hdmi_post_disable()
1462 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_hdmi_post_disable()
1464 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_hdmi_post_disable()
1466 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_hdmi_post_disable()
1468 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_hdmi_post_disable()
1484 	int pipe = intel_crtc->pipe;  in chv_hdmi_pre_enable()  local
1491 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_hdmi_pre_enable()
1493 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_hdmi_pre_enable()
1495 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_hdmi_pre_enable()
1497 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_hdmi_pre_enable()
1500 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_hdmi_pre_enable()
1502 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_hdmi_pre_enable()
1504 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_hdmi_pre_enable()
1506 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_hdmi_pre_enable()
1508 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_hdmi_pre_enable()
1510 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_hdmi_pre_enable()
1512 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_hdmi_pre_enable()
1514 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_hdmi_pre_enable()
1520 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),  in chv_hdmi_pre_enable()
1528 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_hdmi_pre_enable()
1532 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_hdmi_pre_enable()
1534 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_hdmi_pre_enable()
1538 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_hdmi_pre_enable()
1540 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));  in chv_hdmi_pre_enable()
1543 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);  in chv_hdmi_pre_enable()
1545 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));  in chv_hdmi_pre_enable()
1548 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);  in chv_hdmi_pre_enable()
1553 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));  in chv_hdmi_pre_enable()
1556 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);  in chv_hdmi_pre_enable()
1560 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in chv_hdmi_pre_enable()
1563 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in chv_hdmi_pre_enable()
1568 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in chv_hdmi_pre_enable()
1570 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in chv_hdmi_pre_enable()
1575 	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));  in chv_hdmi_pre_enable()
1580 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);  in chv_hdmi_pre_enable()
1582 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),  in chv_hdmi_pre_enable()
1583 			vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |  in chv_hdmi_pre_enable()
1587 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_hdmi_pre_enable()
1589 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_hdmi_pre_enable()
1591 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_hdmi_pre_enable()
1593 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_hdmi_pre_enable()
1596 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);  in chv_hdmi_pre_enable()
1598 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);  in chv_hdmi_pre_enable()