Lines Matching refs:dev_priv
50 struct drm_i915_private *dev_priv = dev->dev_private; in assert_hdmi_port_disabled() local
118 struct drm_i915_private *dev_priv) in hsw_infoframe_data_reg() argument
139 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_write_infoframe() local
173 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_infoframe_enabled() local
189 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_write_infoframe() local
224 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_infoframe_enabled() local
238 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_write_infoframe() local
276 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_infoframe_enabled() local
290 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_write_infoframe() local
325 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_infoframe_enabled() local
339 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_write_infoframe() local
348 dev_priv); in hsw_write_infoframe()
373 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_infoframe_enabled() local
486 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in g4x_set_infoframes() local
540 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in ibx_set_infoframes() local
588 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in cpt_set_infoframes() local
625 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in vlv_set_infoframes() local
673 struct drm_i915_private *dev_priv = encoder->dev->dev_private; in hsw_set_infoframes() local
701 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_prepare() local
738 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_get_hw_state() local
744 if (!intel_display_power_is_enabled(dev_priv, power_domain)) in intel_hdmi_get_hw_state()
767 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_get_config() local
803 if (HAS_PCH_SPLIT(dev_priv->dev)) in intel_hdmi_get_config()
812 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_hdmi() local
864 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_hdmi() local
1074 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_set_edid() local
1083 intel_display_power_get(dev_priv, power_domain); in intel_hdmi_set_edid()
1086 intel_gmbus_get_adapter(dev_priv, in intel_hdmi_set_edid()
1089 intel_display_power_put(dev_priv, power_domain); in intel_hdmi_set_edid()
1181 struct drm_i915_private *dev_priv = connector->dev->dev_private; in intel_hdmi_set_property() local
1188 if (property == dev_priv->force_audio_property) { in intel_hdmi_set_property()
1209 if (property == dev_priv->broadcast_rgb_property) { in intel_hdmi_set_property()
1281 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_hdmi_pre_enable() local
1291 mutex_lock(&dev_priv->dpio_lock); in vlv_hdmi_pre_enable()
1292 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_hdmi_pre_enable()
1299 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_hdmi_pre_enable()
1302 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); in vlv_hdmi_pre_enable()
1303 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); in vlv_hdmi_pre_enable()
1304 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); in vlv_hdmi_pre_enable()
1305 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); in vlv_hdmi_pre_enable()
1306 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); in vlv_hdmi_pre_enable()
1307 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_hdmi_pre_enable()
1308 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_enable()
1309 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_enable()
1312 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_hdmi_pre_enable()
1313 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_hdmi_pre_enable()
1314 mutex_unlock(&dev_priv->dpio_lock); in vlv_hdmi_pre_enable()
1322 vlv_wait_port_ready(dev_priv, dport); in vlv_hdmi_pre_enable()
1329 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_hdmi_pre_pll_enable() local
1338 mutex_lock(&dev_priv->dpio_lock); in vlv_hdmi_pre_pll_enable()
1339 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_hdmi_pre_pll_enable()
1342 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_hdmi_pre_pll_enable()
1349 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_hdmi_pre_pll_enable()
1350 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); in vlv_hdmi_pre_pll_enable()
1351 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); in vlv_hdmi_pre_pll_enable()
1353 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_pll_enable()
1354 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_pll_enable()
1355 mutex_unlock(&dev_priv->dpio_lock); in vlv_hdmi_pre_pll_enable()
1362 struct drm_i915_private *dev_priv = dev->dev_private; in chv_hdmi_pre_pll_enable() local
1371 mutex_lock(&dev_priv->dpio_lock); in chv_hdmi_pre_pll_enable()
1375 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_pre_pll_enable()
1381 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_hdmi_pre_pll_enable()
1383 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_pre_pll_enable()
1389 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_hdmi_pre_pll_enable()
1393 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_hdmi_pre_pll_enable()
1399 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1401 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_hdmi_pre_pll_enable()
1407 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_hdmi_pre_pll_enable()
1414 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_hdmi_pre_pll_enable()
1419 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_hdmi_pre_pll_enable()
1421 mutex_unlock(&dev_priv->dpio_lock); in chv_hdmi_pre_pll_enable()
1427 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; in vlv_hdmi_post_disable() local
1434 mutex_lock(&dev_priv->dpio_lock); in vlv_hdmi_post_disable()
1435 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); in vlv_hdmi_post_disable()
1436 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); in vlv_hdmi_post_disable()
1437 mutex_unlock(&dev_priv->dpio_lock); in vlv_hdmi_post_disable()
1444 struct drm_i915_private *dev_priv = dev->dev_private; in chv_hdmi_post_disable() local
1451 mutex_lock(&dev_priv->dpio_lock); in chv_hdmi_post_disable()
1454 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_hdmi_post_disable()
1456 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_hdmi_post_disable()
1458 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_hdmi_post_disable()
1460 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_hdmi_post_disable()
1462 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_hdmi_post_disable()
1464 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_hdmi_post_disable()
1466 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_hdmi_post_disable()
1468 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_hdmi_post_disable()
1470 mutex_unlock(&dev_priv->dpio_lock); in chv_hdmi_post_disable()
1478 struct drm_i915_private *dev_priv = dev->dev_private; in chv_hdmi_pre_enable() local
1488 mutex_lock(&dev_priv->dpio_lock); in chv_hdmi_pre_enable()
1491 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_hdmi_pre_enable()
1493 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_hdmi_pre_enable()
1495 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_hdmi_pre_enable()
1497 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_hdmi_pre_enable()
1500 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_hdmi_pre_enable()
1502 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_hdmi_pre_enable()
1504 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_hdmi_pre_enable()
1506 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_hdmi_pre_enable()
1508 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_hdmi_pre_enable()
1510 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_hdmi_pre_enable()
1512 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_hdmi_pre_enable()
1514 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_hdmi_pre_enable()
1520 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_hdmi_pre_enable()
1528 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1532 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1534 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1538 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()
1540 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_hdmi_pre_enable()
1543 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_hdmi_pre_enable()
1545 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_hdmi_pre_enable()
1548 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_hdmi_pre_enable()
1553 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_hdmi_pre_enable()
1556 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_hdmi_pre_enable()
1560 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); in chv_hdmi_pre_enable()
1563 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_hdmi_pre_enable()
1568 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); in chv_hdmi_pre_enable()
1570 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_hdmi_pre_enable()
1575 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); in chv_hdmi_pre_enable()
1580 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); in chv_hdmi_pre_enable()
1582 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), in chv_hdmi_pre_enable()
1583 vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | in chv_hdmi_pre_enable()
1587 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_hdmi_pre_enable()
1589 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_hdmi_pre_enable()
1591 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_hdmi_pre_enable()
1593 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_hdmi_pre_enable()
1596 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); in chv_hdmi_pre_enable()
1598 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); in chv_hdmi_pre_enable()
1600 mutex_unlock(&dev_priv->dpio_lock); in chv_hdmi_pre_enable()
1608 vlv_wait_port_ready(dev_priv, dport); in chv_hdmi_pre_enable()
1666 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hdmi_init_connector() local