55 	enum pipe pipe;  in ivb_can_enable_err_int()  local
59 	for_each_pipe(dev_priv, pipe) {  in ivb_can_enable_err_int()
60 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);  in ivb_can_enable_err_int()
72 	enum pipe pipe;  in cpt_can_enable_serr_int()  local
77 	for_each_pipe(dev_priv, pipe) {  in cpt_can_enable_serr_int()
78 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);  in cpt_can_enable_serr_int()
102 		u32 reg = PIPESTAT(crtc->pipe);  in i9xx_check_fifo_underruns()
115 		DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));  in i9xx_check_fifo_underruns()
122 					     enum pipe pipe,  in i9xx_set_fifo_underrun_reporting()  argument
126 	u32 reg = PIPESTAT(pipe);  in i9xx_set_fifo_underrun_reporting()
136 			DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));  in i9xx_set_fifo_underrun_reporting()
141 						 enum pipe pipe, bool enable)  in ironlake_set_fifo_underrun_reporting()  argument
144 	uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :  in ironlake_set_fifo_underrun_reporting()
154 						  enum pipe pipe,  in ivybridge_set_fifo_underrun_reporting()  argument
159 		I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));  in ivybridge_set_fifo_underrun_reporting()
169 		    I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {  in ivybridge_set_fifo_underrun_reporting()
171 				  pipe_name(pipe));  in ivybridge_set_fifo_underrun_reporting()
177 						  enum pipe pipe, bool enable)  in broadwell_set_fifo_underrun_reporting()  argument
184 		dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;  in broadwell_set_fifo_underrun_reporting()
186 		dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;  in broadwell_set_fifo_underrun_reporting()
187 	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);  in broadwell_set_fifo_underrun_reporting()
188 	POSTING_READ(GEN8_DE_PIPE_IMR(pipe));  in broadwell_set_fifo_underrun_reporting()
231 						    enum pipe pipe, bool enable)  in __intel_set_cpu_fifo_underrun_reporting()  argument
234 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];  in __intel_set_cpu_fifo_underrun_reporting()
244 		i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
246 		ironlake_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
248 		ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);  in __intel_set_cpu_fifo_underrun_reporting()
250 		broadwell_set_fifo_underrun_reporting(dev, pipe, enable);  in __intel_set_cpu_fifo_underrun_reporting()
272 					   enum pipe pipe, bool enable)  in intel_set_cpu_fifo_underrun_reporting()  argument
278 	ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe,  in intel_set_cpu_fifo_underrun_reporting()
343 					 enum pipe pipe)  in intel_cpu_fifo_underrun_irq_handler()  argument
345 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];  in intel_cpu_fifo_underrun_irq_handler()
356 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false))  in intel_cpu_fifo_underrun_irq_handler()
358 			  pipe_name(pipe));  in intel_cpu_fifo_underrun_irq_handler()