53 	struct drm_i915_private *dev_priv = dev->dev_private;  in ivb_can_enable_err_int()  local
57 	assert_spin_locked(&dev_priv->irq_lock);  in ivb_can_enable_err_int()
59 	for_each_pipe(dev_priv, pipe) {  in ivb_can_enable_err_int()
60 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);  in ivb_can_enable_err_int()
71 	struct drm_i915_private *dev_priv = dev->dev_private;  in cpt_can_enable_serr_int()  local
75 	assert_spin_locked(&dev_priv->irq_lock);  in cpt_can_enable_serr_int()
77 	for_each_pipe(dev_priv, pipe) {  in cpt_can_enable_serr_int()
78 		crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);  in cpt_can_enable_serr_int()
95 void i9xx_check_fifo_underruns(struct drm_i915_private *dev_priv)  in i9xx_check_fifo_underruns()  argument
99 	spin_lock_irq(&dev_priv->irq_lock);  in i9xx_check_fifo_underruns()
101 	for_each_intel_crtc(dev_priv->dev, crtc) {  in i9xx_check_fifo_underruns()
118 	spin_unlock_irq(&dev_priv->irq_lock);  in i9xx_check_fifo_underruns()
125 	struct drm_i915_private *dev_priv = dev->dev_private;  in i9xx_set_fifo_underrun_reporting()  local
129 	assert_spin_locked(&dev_priv->irq_lock);  in i9xx_set_fifo_underrun_reporting()
143 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_set_fifo_underrun_reporting()  local
148 		ironlake_enable_display_irq(dev_priv, bit);  in ironlake_set_fifo_underrun_reporting()
150 		ironlake_disable_display_irq(dev_priv, bit);  in ironlake_set_fifo_underrun_reporting()
157 	struct drm_i915_private *dev_priv = dev->dev_private;  in ivybridge_set_fifo_underrun_reporting()  local
164 		ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);  in ivybridge_set_fifo_underrun_reporting()
166 		ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);  in ivybridge_set_fifo_underrun_reporting()
179 	struct drm_i915_private *dev_priv = dev->dev_private;  in broadwell_set_fifo_underrun_reporting()  local
181 	assert_spin_locked(&dev_priv->irq_lock);  in broadwell_set_fifo_underrun_reporting()
184 		dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;  in broadwell_set_fifo_underrun_reporting()
186 		dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;  in broadwell_set_fifo_underrun_reporting()
187 	I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);  in broadwell_set_fifo_underrun_reporting()
195 	struct drm_i915_private *dev_priv = dev->dev_private;  in ibx_set_fifo_underrun_reporting()  local
200 		ibx_enable_display_interrupt(dev_priv, bit);  in ibx_set_fifo_underrun_reporting()
202 		ibx_disable_display_interrupt(dev_priv, bit);  in ibx_set_fifo_underrun_reporting()
209 	struct drm_i915_private *dev_priv = dev->dev_private;  in cpt_set_fifo_underrun_reporting()  local
218 		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);  in cpt_set_fifo_underrun_reporting()
220 		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);  in cpt_set_fifo_underrun_reporting()
233 	struct drm_i915_private *dev_priv = dev->dev_private;  in __intel_set_cpu_fifo_underrun_reporting()  local
234 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];  in __intel_set_cpu_fifo_underrun_reporting()
238 	assert_spin_locked(&dev_priv->irq_lock);  in __intel_set_cpu_fifo_underrun_reporting()
271 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,  in intel_set_cpu_fifo_underrun_reporting()  argument
277 	spin_lock_irqsave(&dev_priv->irq_lock, flags);  in intel_set_cpu_fifo_underrun_reporting()
278 	ret = __intel_set_cpu_fifo_underrun_reporting(dev_priv->dev, pipe,  in intel_set_cpu_fifo_underrun_reporting()
280 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);  in intel_set_cpu_fifo_underrun_reporting()
299 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,  in intel_set_pch_fifo_underrun_reporting()  argument
303 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];  in intel_set_pch_fifo_underrun_reporting()
317 	spin_lock_irqsave(&dev_priv->irq_lock, flags);  in intel_set_pch_fifo_underrun_reporting()
322 	if (HAS_PCH_IBX(dev_priv->dev))  in intel_set_pch_fifo_underrun_reporting()
323 		ibx_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,  in intel_set_pch_fifo_underrun_reporting()
326 		cpt_set_fifo_underrun_reporting(dev_priv->dev, pch_transcoder,  in intel_set_pch_fifo_underrun_reporting()
329 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);  in intel_set_pch_fifo_underrun_reporting()
342 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,  in intel_cpu_fifo_underrun_irq_handler()  argument
345 	struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];  in intel_cpu_fifo_underrun_irq_handler()
352 	if (HAS_GMCH_DISPLAY(dev_priv->dev) &&  in intel_cpu_fifo_underrun_irq_handler()
356 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false))  in intel_cpu_fifo_underrun_irq_handler()
370 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,  in intel_pch_fifo_underrun_irq_handler()  argument
373 	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,  in intel_pch_fifo_underrun_irq_handler()