Lines Matching refs:dev_priv
46 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_fbc_disable() local
49 dev_priv->fbc.enabled = false; in i8xx_fbc_disable()
71 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_fbc_enable() local
79 dev_priv->fbc.enabled = true; in i8xx_fbc_enable()
82 cfb_pitch = dev_priv->fbc.uncompressed_size / FBC_LL_SIZE; in i8xx_fbc_enable()
122 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_fbc_enabled() local
130 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_fbc_enable() local
136 dev_priv->fbc.enabled = true; in g4x_fbc_enable()
155 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_fbc_disable() local
158 dev_priv->fbc.enabled = false; in g4x_fbc_disable()
172 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_fbc_enabled() local
177 static void intel_fbc_nuke(struct drm_i915_private *dev_priv) in intel_fbc_nuke() argument
186 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_fbc_enable() local
192 dev_priv->fbc.enabled = true; in ilk_fbc_enable()
196 dev_priv->fbc.threshold++; in ilk_fbc_enable()
198 switch (dev_priv->fbc.threshold) { in ilk_fbc_enable()
225 intel_fbc_nuke(dev_priv); in ilk_fbc_enable()
232 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_fbc_disable() local
235 dev_priv->fbc.enabled = false; in ilk_fbc_disable()
249 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_fbc_enabled() local
257 struct drm_i915_private *dev_priv = dev->dev_private; in gen7_fbc_enable() local
263 dev_priv->fbc.enabled = true; in gen7_fbc_enable()
267 dev_priv->fbc.threshold++; in gen7_fbc_enable()
269 switch (dev_priv->fbc.threshold) { in gen7_fbc_enable()
284 if (dev_priv->fbc.false_color) in gen7_fbc_enable()
305 intel_fbc_nuke(dev_priv); in gen7_fbc_enable()
320 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fbc_enabled() local
322 return dev_priv->fbc.enabled; in intel_fbc_enabled()
331 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fbc_work_fn() local
334 if (work == dev_priv->fbc.fbc_work) { in intel_fbc_work_fn()
339 dev_priv->display.enable_fbc(work->crtc); in intel_fbc_work_fn()
341 dev_priv->fbc.crtc = to_intel_crtc(work->crtc); in intel_fbc_work_fn()
342 dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; in intel_fbc_work_fn()
343 dev_priv->fbc.y = work->crtc->y; in intel_fbc_work_fn()
346 dev_priv->fbc.fbc_work = NULL; in intel_fbc_work_fn()
353 static void intel_fbc_cancel_work(struct drm_i915_private *dev_priv) in intel_fbc_cancel_work() argument
355 if (dev_priv->fbc.fbc_work == NULL) in intel_fbc_cancel_work()
364 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) in intel_fbc_cancel_work()
366 kfree(dev_priv->fbc.fbc_work); in intel_fbc_cancel_work()
373 dev_priv->fbc.fbc_work = NULL; in intel_fbc_cancel_work()
380 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fbc_enable() local
382 if (!dev_priv->display.enable_fbc) in intel_fbc_enable()
385 intel_fbc_cancel_work(dev_priv); in intel_fbc_enable()
390 dev_priv->display.enable_fbc(crtc); in intel_fbc_enable()
398 dev_priv->fbc.fbc_work = work; in intel_fbc_enable()
424 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fbc_disable() local
426 intel_fbc_cancel_work(dev_priv); in intel_fbc_disable()
428 if (!dev_priv->display.disable_fbc) in intel_fbc_disable()
431 dev_priv->display.disable_fbc(dev); in intel_fbc_disable()
432 dev_priv->fbc.crtc = NULL; in intel_fbc_disable()
435 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, in set_no_fbc_reason() argument
438 if (dev_priv->fbc.no_fbc_reason == reason) in set_no_fbc_reason()
441 dev_priv->fbc.no_fbc_reason = reason; in set_no_fbc_reason()
445 static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) in intel_fbc_find_crtc() argument
451 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) in intel_fbc_find_crtc()
453 else if (INTEL_INFO(dev_priv)->gen <= 4) in intel_fbc_find_crtc()
456 for_each_pipe(dev_priv, pipe) { in intel_fbc_find_crtc()
457 tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_fbc_find_crtc()
462 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) in intel_fbc_find_crtc()
474 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) in intel_fbc_find_crtc()
503 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fbc_update() local
519 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) in intel_fbc_update()
525 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) in intel_fbc_update()
539 crtc = intel_fbc_find_crtc(dev_priv); in intel_fbc_update()
550 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) in intel_fbc_update()
568 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) in intel_fbc_update()
574 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) in intel_fbc_update()
584 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) in intel_fbc_update()
590 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) in intel_fbc_update()
601 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) in intel_fbc_update()
611 if (dev_priv->fbc.crtc == intel_crtc && in intel_fbc_update()
612 dev_priv->fbc.fb_id == fb->base.id && in intel_fbc_update()
613 dev_priv->fbc.y == crtc->y) in intel_fbc_update()
645 dev_priv->fbc.no_fbc_reason = FBC_OK; in intel_fbc_update()
657 void intel_fbc_invalidate(struct drm_i915_private *dev_priv, in intel_fbc_invalidate() argument
661 struct drm_device *dev = dev_priv->dev; in intel_fbc_invalidate()
667 if (dev_priv->fbc.enabled) in intel_fbc_invalidate()
668 fbc_bits = INTEL_FRONTBUFFER_PRIMARY(dev_priv->fbc.crtc->pipe); in intel_fbc_invalidate()
669 else if (dev_priv->fbc.fbc_work) in intel_fbc_invalidate()
671 to_intel_crtc(dev_priv->fbc.fbc_work->crtc)->pipe); in intel_fbc_invalidate()
673 fbc_bits = dev_priv->fbc.possible_framebuffer_bits; in intel_fbc_invalidate()
675 dev_priv->fbc.busy_bits |= (fbc_bits & frontbuffer_bits); in intel_fbc_invalidate()
677 if (dev_priv->fbc.busy_bits) in intel_fbc_invalidate()
681 void intel_fbc_flush(struct drm_i915_private *dev_priv, in intel_fbc_flush() argument
684 struct drm_device *dev = dev_priv->dev; in intel_fbc_flush()
686 if (!dev_priv->fbc.busy_bits) in intel_fbc_flush()
689 dev_priv->fbc.busy_bits &= ~frontbuffer_bits; in intel_fbc_flush()
691 if (!dev_priv->fbc.busy_bits) in intel_fbc_flush()
701 void intel_fbc_init(struct drm_i915_private *dev_priv) in intel_fbc_init() argument
705 if (!HAS_FBC(dev_priv)) { in intel_fbc_init()
706 dev_priv->fbc.enabled = false; in intel_fbc_init()
707 dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED; in intel_fbc_init()
711 for_each_pipe(dev_priv, pipe) { in intel_fbc_init()
712 dev_priv->fbc.possible_framebuffer_bits |= in intel_fbc_init()
715 if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) in intel_fbc_init()
719 if (INTEL_INFO(dev_priv)->gen >= 7) { in intel_fbc_init()
720 dev_priv->display.fbc_enabled = ilk_fbc_enabled; in intel_fbc_init()
721 dev_priv->display.enable_fbc = gen7_fbc_enable; in intel_fbc_init()
722 dev_priv->display.disable_fbc = ilk_fbc_disable; in intel_fbc_init()
723 } else if (INTEL_INFO(dev_priv)->gen >= 5) { in intel_fbc_init()
724 dev_priv->display.fbc_enabled = ilk_fbc_enabled; in intel_fbc_init()
725 dev_priv->display.enable_fbc = ilk_fbc_enable; in intel_fbc_init()
726 dev_priv->display.disable_fbc = ilk_fbc_disable; in intel_fbc_init()
727 } else if (IS_GM45(dev_priv)) { in intel_fbc_init()
728 dev_priv->display.fbc_enabled = g4x_fbc_enabled; in intel_fbc_init()
729 dev_priv->display.enable_fbc = g4x_fbc_enable; in intel_fbc_init()
730 dev_priv->display.disable_fbc = g4x_fbc_disable; in intel_fbc_init()
732 dev_priv->display.fbc_enabled = i8xx_fbc_enabled; in intel_fbc_init()
733 dev_priv->display.enable_fbc = i8xx_fbc_enable; in intel_fbc_init()
734 dev_priv->display.disable_fbc = i8xx_fbc_disable; in intel_fbc_init()
740 dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev); in intel_fbc_init()