Lines Matching refs:port
48 static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) in wait_for_dsi_fifo_empty() argument
58 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) in wait_for_dsi_fifo_empty()
96 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer() local
110 data_reg = MIPI_LP_GEN_DATA(port); in intel_dsi_host_transfer()
112 ctrl_reg = MIPI_LP_GEN_CTRL(port); in intel_dsi_host_transfer()
115 data_reg = MIPI_HS_GEN_DATA(port); in intel_dsi_host_transfer()
117 ctrl_reg = MIPI_HS_GEN_CTRL(port); in intel_dsi_host_transfer()
124 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) in intel_dsi_host_transfer()
132 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); in intel_dsi_host_transfer()
135 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { in intel_dsi_host_transfer()
144 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) in intel_dsi_host_transfer()
173 enum port port) in intel_dsi_host_init() argument
184 host->port = port; in intel_dsi_host_init()
211 enum port port) in dpi_send_cmd() argument
225 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
228 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
231 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
234 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) in dpi_send_cmd()
295 enum port port; in intel_dsi_port_enable() local
306 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
307 temp = I915_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_enable()
319 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); in intel_dsi_port_enable()
320 POSTING_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_enable()
329 enum port port; in intel_dsi_port_disable() local
332 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_disable()
334 temp = I915_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_disable()
335 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); in intel_dsi_port_disable()
336 POSTING_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_disable()
344 enum port port; in intel_dsi_device_ready() local
358 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_device_ready()
360 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); in intel_dsi_device_ready()
371 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); in intel_dsi_device_ready()
374 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); in intel_dsi_device_ready()
384 enum port port; in intel_dsi_enable() local
389 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_enable()
390 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); in intel_dsi_enable()
393 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_enable()
394 dpi_send_cmd(intel_dsi, TURN_ON, false, port); in intel_dsi_enable()
399 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_enable()
400 wait_for_dsi_fifo_empty(intel_dsi, port); in intel_dsi_enable()
413 enum port port; in intel_dsi_pre_enable() local
439 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
440 wait_for_dsi_fifo_empty(intel_dsi, port); in intel_dsi_pre_enable()
460 enum port port; in intel_dsi_pre_disable() local
466 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_disable()
467 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); in intel_dsi_pre_disable()
477 enum port port; in intel_dsi_disable() local
483 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_disable()
484 wait_for_dsi_fifo_empty(intel_dsi, port); in intel_dsi_disable()
490 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_disable()
492 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); in intel_dsi_disable()
494 temp = I915_READ(MIPI_CTRL(port)); in intel_dsi_disable()
496 I915_WRITE(MIPI_CTRL(port), temp | in intel_dsi_disable()
500 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); in intel_dsi_disable()
502 temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); in intel_dsi_disable()
504 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); in intel_dsi_disable()
506 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); in intel_dsi_disable()
512 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_disable()
513 wait_for_dsi_fifo_empty(intel_dsi, port); in intel_dsi_disable()
520 enum port port; in intel_dsi_clear_device_ready() local
524 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_clear_device_ready()
526 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in intel_dsi_clear_device_ready()
530 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in intel_dsi_clear_device_ready()
534 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in intel_dsi_clear_device_ready()
552 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); in intel_dsi_clear_device_ready()
589 enum port port; in intel_dsi_get_hw_state() local
598 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_get_hw_state()
599 func = I915_READ(MIPI_DSI_FUNC_PRG(port)); in intel_dsi_get_hw_state()
600 dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) & in intel_dsi_get_hw_state()
608 (port == PORT_C)) in intel_dsi_get_hw_state()
613 if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { in intel_dsi_get_hw_state()
614 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
696 enum port port; in set_dsi_timings() local
728 for_each_dsi_port(port, intel_dsi->ports) { in set_dsi_timings()
729 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); in set_dsi_timings()
730 I915_WRITE(MIPI_HFP_COUNT(port), hfp); in set_dsi_timings()
734 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); in set_dsi_timings()
735 I915_WRITE(MIPI_HBP_COUNT(port), hbp); in set_dsi_timings()
738 I915_WRITE(MIPI_VFP_COUNT(port), vfp); in set_dsi_timings()
739 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); in set_dsi_timings()
740 I915_WRITE(MIPI_VBP_COUNT(port), vbp); in set_dsi_timings()
753 enum port port; in intel_dsi_prepare() local
768 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
776 tmp = I915_READ(MIPI_CTRL(port)); in intel_dsi_prepare()
778 I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); in intel_dsi_prepare()
781 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); in intel_dsi_prepare()
782 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); in intel_dsi_prepare()
784 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); in intel_dsi_prepare()
786 I915_WRITE(MIPI_DPI_RESOLUTION(port), in intel_dsi_prepare()
810 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
811 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_prepare()
832 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
837 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
843 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
844 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), in intel_dsi_prepare()
846 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), in intel_dsi_prepare()
852 I915_WRITE(MIPI_INIT_COUNT(port), in intel_dsi_prepare()
857 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); in intel_dsi_prepare()
860 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); in intel_dsi_prepare()
867 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), in intel_dsi_prepare()
876 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); in intel_dsi_prepare()
883 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); in intel_dsi_prepare()
885 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), in intel_dsi_prepare()
893 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), in intel_dsi_prepare()
990 enum port port; in intel_dsi_init() local
1039 if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { in intel_dsi_init()
1042 } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { in intel_dsi_init()
1051 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_init()
1054 host = intel_dsi_host_init(intel_dsi, port); in intel_dsi_init()
1058 intel_dsi->dsi_hosts[port] = host; in intel_dsi_init()