Lines Matching refs:I915_WRITE
73 I915_WRITE(reg, val); in write_data()
132 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); in intel_dsi_host_transfer()
139 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); in intel_dsi_host_transfer()
225 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); in dpi_send_cmd()
231 I915_WRITE(MIPI_DPI_CONTROL(port), cmd); in dpi_send_cmd()
303 I915_WRITE(VLV_CHICKEN_3, temp); in intel_dsi_port_enable()
319 I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); in intel_dsi_port_enable()
335 I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); in intel_dsi_port_disable()
360 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); in intel_dsi_device_ready()
368 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); in intel_dsi_device_ready()
371 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); in intel_dsi_device_ready()
374 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); in intel_dsi_device_ready()
390 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); in intel_dsi_enable()
422 I915_WRITE(DPLL(pipe), tmp); in intel_dsi_pre_enable()
430 I915_WRITE(DSPCLK_GATE_D, tmp); in intel_dsi_pre_enable()
492 I915_WRITE(MIPI_DEVICE_READY(port), 0x0); in intel_dsi_disable()
496 I915_WRITE(MIPI_CTRL(port), temp | in intel_dsi_disable()
500 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); in intel_dsi_disable()
504 I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); in intel_dsi_disable()
506 I915_WRITE(MIPI_DEVICE_READY(port), 0x1); in intel_dsi_disable()
526 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in intel_dsi_clear_device_ready()
530 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in intel_dsi_clear_device_ready()
534 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | in intel_dsi_clear_device_ready()
549 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); in intel_dsi_clear_device_ready()
552 I915_WRITE(MIPI_DEVICE_READY(port), 0x00); in intel_dsi_clear_device_ready()
573 I915_WRITE(DSPCLK_GATE_D, val); in intel_dsi_post_disable()
729 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); in set_dsi_timings()
730 I915_WRITE(MIPI_HFP_COUNT(port), hfp); in set_dsi_timings()
734 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); in set_dsi_timings()
735 I915_WRITE(MIPI_HBP_COUNT(port), hbp); in set_dsi_timings()
738 I915_WRITE(MIPI_VFP_COUNT(port), vfp); in set_dsi_timings()
739 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); in set_dsi_timings()
740 I915_WRITE(MIPI_VBP_COUNT(port), vbp); in set_dsi_timings()
773 I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); in intel_dsi_prepare()
778 I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); in intel_dsi_prepare()
781 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); in intel_dsi_prepare()
782 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); in intel_dsi_prepare()
784 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); in intel_dsi_prepare()
786 I915_WRITE(MIPI_DPI_RESOLUTION(port), in intel_dsi_prepare()
811 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); in intel_dsi_prepare()
832 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
837 I915_WRITE(MIPI_HS_TX_TIMEOUT(port), in intel_dsi_prepare()
843 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
844 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), in intel_dsi_prepare()
846 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), in intel_dsi_prepare()
852 I915_WRITE(MIPI_INIT_COUNT(port), in intel_dsi_prepare()
857 I915_WRITE(MIPI_EOT_DISABLE(port), tmp); in intel_dsi_prepare()
860 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); in intel_dsi_prepare()
867 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), in intel_dsi_prepare()
876 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); in intel_dsi_prepare()
883 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); in intel_dsi_prepare()
885 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), in intel_dsi_prepare()
893 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), in intel_dsi_prepare()