1693 	u32 pp;  in edp_panel_vdd_on()  local
1717 	pp = ironlake_get_pp_control(intel_dp);  in edp_panel_vdd_on()
1718 	pp |= EDP_FORCE_VDD;  in edp_panel_vdd_on()
1723 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_vdd_on()
1769 	u32 pp;  in edp_panel_vdd_off_sync()  local
1782 	pp = ironlake_get_pp_control(intel_dp);  in edp_panel_vdd_off_sync()
1783 	pp &= ~EDP_FORCE_VDD;  in edp_panel_vdd_off_sync()
1788 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_vdd_off_sync()
1795 	if ((pp & POWER_TARGET_ON) == 0)  in edp_panel_vdd_off_sync()
1856 	u32 pp;  in edp_panel_on()  local
1875 	pp = ironlake_get_pp_control(intel_dp);  in edp_panel_on()
1878 		pp &= ~PANEL_POWER_RESET;  in edp_panel_on()
1879 		I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_on()
1883 	pp |= POWER_TARGET_ON;  in edp_panel_on()
1885 		pp |= PANEL_POWER_RESET;  in edp_panel_on()
1887 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_on()
1894 		pp |= PANEL_POWER_RESET; /* restore panel reset bit */  in edp_panel_on()
1895 		I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_on()
1918 	u32 pp;  in edp_panel_off()  local
1932 	pp = ironlake_get_pp_control(intel_dp);  in edp_panel_off()
1935 	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |  in edp_panel_off()
1942 	I915_WRITE(pp_ctrl_reg, pp);  in edp_panel_off()
1969 	u32 pp;  in _intel_edp_backlight_on()  local
1982 	pp = ironlake_get_pp_control(intel_dp);  in _intel_edp_backlight_on()
1983 	pp |= EDP_BLC_ENABLE;  in _intel_edp_backlight_on()
1987 	I915_WRITE(pp_ctrl_reg, pp);  in _intel_edp_backlight_on()
2010 	u32 pp;  in _intel_edp_backlight_off()  local
2018 	pp = ironlake_get_pp_control(intel_dp);  in _intel_edp_backlight_off()
2019 	pp &= ~EDP_BLC_ENABLE;  in _intel_edp_backlight_off()
2023 	I915_WRITE(pp_ctrl_reg, pp);  in _intel_edp_backlight_off()
4810 	u32 pp_on, pp_off, pp_div, pp;  in intel_dp_init_panel_power_sequencer()  local
4835 	pp = ironlake_get_pp_control(intel_dp);  in intel_dp_init_panel_power_sequencer()
4836 	I915_WRITE(pp_ctrl_reg, pp);  in intel_dp_init_panel_power_sequencer()