126 				      enum pipe pipe);
330 	enum pipe pipe = intel_dp->pps_pipe;  in vlv_power_sequencer_kick()  local
336 		 pipe_name(pipe), port_name(intel_dig_port->port)))  in vlv_power_sequencer_kick()
340 		      pipe_name(pipe), port_name(intel_dig_port->port));  in vlv_power_sequencer_kick()
351 		DP |= DP_PIPE_SELECT_CHV(pipe);  in vlv_power_sequencer_kick()
352 	else if (pipe == PIPE_B)  in vlv_power_sequencer_kick()
355 	pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;  in vlv_power_sequencer_kick()
362 		vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?  in vlv_power_sequencer_kick()
381 		vlv_force_pll_off(dev, pipe);  in vlv_power_sequencer_kick()
384 static enum pipe
392 	enum pipe pipe;  in vlv_power_sequencer_pipe()  local
424 		pipe = PIPE_A;  in vlv_power_sequencer_pipe()
426 		pipe = ffs(pipes) - 1;  in vlv_power_sequencer_pipe()
428 	vlv_steal_power_sequencer(dev, pipe);  in vlv_power_sequencer_pipe()
429 	intel_dp->pps_pipe = pipe;  in vlv_power_sequencer_pipe()
449 			       enum pipe pipe);
452 			       enum pipe pipe)  in vlv_pipe_has_pp_on()  argument
454 	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;  in vlv_pipe_has_pp_on()
458 				enum pipe pipe)  in vlv_pipe_has_vdd_on()  argument
460 	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;  in vlv_pipe_has_vdd_on()
464 			 enum pipe pipe)  in vlv_pipe_any()  argument
469 static enum pipe
474 	enum pipe pipe;  in vlv_initial_pps_pipe()  local
476 	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {  in vlv_initial_pps_pipe()
477 		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &  in vlv_initial_pps_pipe()
483 		if (!pipe_check(dev_priv, pipe))  in vlv_initial_pps_pipe()
486 		return pipe;  in vlv_initial_pps_pipe()
596 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);  in edp_notify_handler()  local
598 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);  in edp_notify_handler()
599 		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);  in edp_notify_handler()
1566 		intel_dp->DP |= crtc->pipe << 29;  in intel_dp_prepare()
1581 			if (crtc->pipe == 1)  in intel_dp_prepare()
1584 			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);  in intel_dp_prepare()
2079 			     to_intel_crtc(crtc)->pipe);  in ironlake_edp_pll_on()
2105 			     to_intel_crtc(crtc)->pipe);  in ironlake_edp_pll_off()
2153 				  enum pipe *pipe)  in intel_dp_get_hw_state()  argument
2172 		*pipe = PORT_TO_PIPE_CPT(tmp);  in intel_dp_get_hw_state()
2174 		*pipe = DP_PORT_TO_PIPE_CHV(tmp);  in intel_dp_get_hw_state()
2176 		*pipe = PORT_TO_PIPE(tmp);  in intel_dp_get_hw_state()
2199 				*pipe = i;  in intel_dp_get_hw_state()
2237 		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));  in intel_dp_get_config()
2345 	enum pipe pipe = intel_crtc->pipe;  in chv_post_disable_dp()  local
2353 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_post_disable_dp()
2355 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_post_disable_dp()
2357 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_post_disable_dp()
2359 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_post_disable_dp()
2361 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_post_disable_dp()
2363 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_post_disable_dp()
2365 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_post_disable_dp()
2367 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_post_disable_dp()
2513 				 pipe_name(crtc->pipe));  in intel_enable_dp()
2552 	enum pipe pipe = intel_dp->pps_pipe;  in vlv_detach_power_sequencer()  local
2553 	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);  in vlv_detach_power_sequencer()
2567 		      pipe_name(pipe), port_name(intel_dig_port->port));  in vlv_detach_power_sequencer()
2575 				      enum pipe pipe)  in vlv_steal_power_sequencer()  argument
2582 	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))  in vlv_steal_power_sequencer()
2596 		if (intel_dp->pps_pipe != pipe)  in vlv_steal_power_sequencer()
2600 			      pipe_name(pipe), port_name(port));  in vlv_steal_power_sequencer()
2604 		     pipe_name(pipe), port_name(port));  in vlv_steal_power_sequencer()
2624 	if (intel_dp->pps_pipe == crtc->pipe)  in vlv_init_panel_power_sequencer()
2639 	vlv_steal_power_sequencer(dev, crtc->pipe);  in vlv_init_panel_power_sequencer()
2642 	intel_dp->pps_pipe = crtc->pipe;  in vlv_init_panel_power_sequencer()
2660 	int pipe = intel_crtc->pipe;  in vlv_pre_enable_dp()  local
2665 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));  in vlv_pre_enable_dp()
2667 	if (pipe)  in vlv_pre_enable_dp()
2672 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);  in vlv_pre_enable_dp()
2673 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);  in vlv_pre_enable_dp()
2674 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);  in vlv_pre_enable_dp()
2689 	int pipe = intel_crtc->pipe;  in vlv_dp_pre_pll_enable()  local
2695 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),  in vlv_dp_pre_pll_enable()
2698 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),  in vlv_dp_pre_pll_enable()
2705 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);  in vlv_dp_pre_pll_enable()
2706 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);  in vlv_dp_pre_pll_enable()
2707 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);  in vlv_dp_pre_pll_enable()
2720 	int pipe = intel_crtc->pipe;  in chv_pre_enable_dp()  local
2727 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_pre_enable_dp()
2729 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_pre_enable_dp()
2731 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_pre_enable_dp()
2733 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_pre_enable_dp()
2736 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_pre_enable_dp()
2738 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_pre_enable_dp()
2740 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_pre_enable_dp()
2742 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_pre_enable_dp()
2744 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_pre_enable_dp()
2746 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_pre_enable_dp()
2748 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_pre_enable_dp()
2750 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_pre_enable_dp()
2756 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),  in chv_pre_enable_dp()
2776 	enum pipe pipe = intel_crtc->pipe;  in chv_dp_pre_pll_enable()  local
2784 	if (pipe != PIPE_B) {  in chv_dp_pre_pll_enable()
2785 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_dp_pre_pll_enable()
2791 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_dp_pre_pll_enable()
2793 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_dp_pre_pll_enable()
2799 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_dp_pre_pll_enable()
2803 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));  in chv_dp_pre_pll_enable()
2805 	if (pipe != PIPE_B)  in chv_dp_pre_pll_enable()
2809 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);  in chv_dp_pre_pll_enable()
2811 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));  in chv_dp_pre_pll_enable()
2813 	if (pipe != PIPE_B)  in chv_dp_pre_pll_enable()
2817 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);  in chv_dp_pre_pll_enable()
2824 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));  in chv_dp_pre_pll_enable()
2825 	if (pipe != PIPE_B)  in chv_dp_pre_pll_enable()
2829 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);  in chv_dp_pre_pll_enable()
2979 	int pipe = intel_crtc->pipe;  in intel_vlv_signal_levels()  local
3055 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);  in intel_vlv_signal_levels()
3056 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);  in intel_vlv_signal_levels()
3057 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),  in intel_vlv_signal_levels()
3059 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);  in intel_vlv_signal_levels()
3060 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);  in intel_vlv_signal_levels()
3061 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);  in intel_vlv_signal_levels()
3062 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);  in intel_vlv_signal_levels()
3077 	enum pipe pipe = intel_crtc->pipe;  in intel_chv_signal_levels()  local
3153 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in intel_chv_signal_levels()
3157 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in intel_chv_signal_levels()
3159 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in intel_chv_signal_levels()
3163 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in intel_chv_signal_levels()
3165 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));  in intel_chv_signal_levels()
3168 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);  in intel_chv_signal_levels()
3170 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));  in intel_chv_signal_levels()
3173 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);  in intel_chv_signal_levels()
3177 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));  in intel_chv_signal_levels()
3180 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);  in intel_chv_signal_levels()
3185 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in intel_chv_signal_levels()
3188 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in intel_chv_signal_levels()
3193 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in intel_chv_signal_levels()
3195 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in intel_chv_signal_levels()
3210 			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in intel_chv_signal_levels()
3212 			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in intel_chv_signal_levels()
3216 			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in intel_chv_signal_levels()
3219 			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in intel_chv_signal_levels()
3224 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in intel_chv_signal_levels()
3226 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in intel_chv_signal_levels()
3228 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in intel_chv_signal_levels()
3230 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in intel_chv_signal_levels()
3233 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);  in intel_chv_signal_levels()
3235 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);  in intel_chv_signal_levels()
3925 		intel_wait_for_vblank(dev, intel_crtc->pipe);  in intel_dp_sink_crc()
4825 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);  in intel_dp_init_panel_power_sequencer()  local
4827 		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);  in intel_dp_init_panel_power_sequencer()
4828 		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer()
4829 		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer()
4830 		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);  in intel_dp_init_panel_power_sequencer()
4924 		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);  in intel_dp_init_panel_power_sequencer_registers()  local
4926 		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer_registers()
4927 		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);  in intel_dp_init_panel_power_sequencer_registers()
4928 		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);  in intel_dp_init_panel_power_sequencer_registers()
5188 	enum pipe pipe;  in intel_edp_drrs_invalidate()  local
5202 	pipe = to_intel_crtc(crtc)->pipe;  in intel_edp_drrs_invalidate()
5210 	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);  in intel_edp_drrs_invalidate()
5232 	enum pipe pipe;  in intel_edp_drrs_flush()  local
5246 	pipe = to_intel_crtc(crtc)->pipe;  in intel_edp_drrs_flush()
5356 	enum pipe pipe = INVALID_PIPE;  in intel_edp_init_connector()  local
5429 			pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);  in intel_edp_init_connector()
5431 			pipe = PORT_TO_PIPE(intel_dp->DP);  in intel_edp_init_connector()
5433 		if (pipe != PIPE_A && pipe != PIPE_B)  in intel_edp_init_connector()
5434 			pipe = intel_dp->pps_pipe;  in intel_edp_init_connector()
5436 		if (pipe != PIPE_A && pipe != PIPE_B)  in intel_edp_init_connector()
5437 			pipe = PIPE_A;  in intel_edp_init_connector()
5440 			      pipe_name(pipe));  in intel_edp_init_connector()
5445 	intel_panel_setup_backlight(connector, pipe);  in intel_edp_init_connector()