1337 	int lane_count, clock;  in intel_dp_compute_config()  local
1407 			for (lane_count = min_lane_count;  in intel_dp_compute_config()
1408 				lane_count <= max_lane_count;  in intel_dp_compute_config()
1409 				lane_count <<= 1) {  in intel_dp_compute_config()
1413 								    lane_count);  in intel_dp_compute_config()
1440 	intel_dp->lane_count = lane_count;  in intel_dp_compute_config()
1456 		      intel_dp->link_bw, intel_dp->lane_count,  in intel_dp_compute_config()
1461 	intel_link_compute_m_n(bpp, lane_count,  in intel_dp_compute_config()
1469 			intel_link_compute_m_n(bpp, lane_count,  in intel_dp_compute_config()
1549 	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);  in intel_dp_prepare()
3252 	for (lane = 0; lane < intel_dp->lane_count; lane++) {  in intel_get_adjust_train()
3466 		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);  in intel_dp_set_link_train()
3467 		len = intel_dp->lane_count + 1;  in intel_dp_set_link_train()
3501 				intel_dp->train_set, intel_dp->lane_count);  in intel_dp_update_link_train()
3503 	return ret == intel_dp->lane_count;  in intel_dp_update_link_train()
3554 	link_config[1] = intel_dp->lane_count;  in intel_dp_start_link_train()
3588 		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {  in intel_dp_start_link_train()
3594 		for (i = 0; i < intel_dp->lane_count; i++)  in intel_dp_start_link_train()
3597 		if (i == intel_dp->lane_count) {  in intel_dp_start_link_train()
3669 		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {  in intel_dp_complete_link_train()
3678 		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {  in intel_dp_complete_link_train()
3989 			if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {  in intel_dp_check_mst_status()
4082 	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {  in intel_dp_check_link_status()