255 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_hrawclk()  local
297 	struct drm_i915_private *dev_priv = dev->dev_private;  in pps_lock()  local
305 	intel_display_power_get(dev_priv, power_domain);  in pps_lock()
307 	mutex_lock(&dev_priv->pps_mutex);  in pps_lock()
315 	struct drm_i915_private *dev_priv = dev->dev_private;  in pps_unlock()  local
318 	mutex_unlock(&dev_priv->pps_mutex);  in pps_unlock()
321 	intel_display_power_put(dev_priv, power_domain);  in pps_unlock()
329 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_power_sequencer_kick()  local
389 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_power_sequencer_pipe()  local
394 	lockdep_assert_held(&dev_priv->pps_mutex);  in vlv_power_sequencer_pipe()
448 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
451 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,  in vlv_pipe_has_pp_on()  argument
457 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,  in vlv_pipe_has_vdd_on()  argument
463 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,  in vlv_pipe_any()  argument
470 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,  in vlv_initial_pps_pipe()  argument
483 		if (!pipe_check(dev_priv, pipe))  in vlv_initial_pps_pipe()
497 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_initial_power_sequencer_setup()  local
500 	lockdep_assert_held(&dev_priv->pps_mutex);  in vlv_initial_power_sequencer_setup()
504 	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,  in vlv_initial_power_sequencer_setup()
508 		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,  in vlv_initial_power_sequencer_setup()
512 		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,  in vlv_initial_power_sequencer_setup()
529 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)  in vlv_power_sequencer_reset()  argument
531 	struct drm_device *dev = dev_priv->dev;  in vlv_power_sequencer_reset()
586 	struct drm_i915_private *dev_priv = dev->dev_private;  in edp_notify_handler()  local
617 	struct drm_i915_private *dev_priv = dev->dev_private;  in edp_have_panel_power()  local
619 	lockdep_assert_held(&dev_priv->pps_mutex);  in edp_have_panel_power()
631 	struct drm_i915_private *dev_priv = dev->dev_private;  in edp_have_panel_vdd()  local
633 	lockdep_assert_held(&dev_priv->pps_mutex);  in edp_have_panel_vdd()
646 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_check_edp()  local
664 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_aux_wait_done()  local
671 		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,  in intel_dp_aux_wait_done()
717 	struct drm_i915_private *dev_priv = dev->dev_private;  in hsw_get_aux_clock_divider()  local
722 		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);  in hsw_get_aux_clock_divider()
723 	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {  in hsw_get_aux_clock_divider()
802 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_aux_ch()  local
826 	pm_qos_update_request(&dev_priv->pm_qos, 0);  in intel_dp_aux_ch()
830 	intel_aux_display_runtime_get(dev_priv);  in intel_dp_aux_ch()
923 	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);  in intel_dp_aux_ch()
924 	intel_aux_display_runtime_put(dev_priv);  in intel_dp_aux_ch()
1331 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_compute_config()  local
1385 		if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {  in intel_dp_compute_config()
1387 				      dev_priv->vbt.edp_bpp);  in intel_dp_compute_config()
1388 			bpp = dev_priv->vbt.edp_bpp;  in intel_dp_compute_config()
1467 		dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {  in intel_dp_compute_config()
1490 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_set_pll_cpu_edp()  local
1519 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_prepare()  local
1605 	struct drm_i915_private *dev_priv = dev->dev_private;  in wait_panel_status()  local
1608 	lockdep_assert_held(&dev_priv->pps_mutex);  in wait_panel_status()
1670 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_get_pp_control()  local
1673 	lockdep_assert_held(&dev_priv->pps_mutex);  in ironlake_get_pp_control()
1691 	struct drm_i915_private *dev_priv = dev->dev_private;  in edp_panel_vdd_on()  local
1697 	lockdep_assert_held(&dev_priv->pps_mutex);  in edp_panel_vdd_on()
1709 	intel_display_power_get(dev_priv, power_domain);  in edp_panel_vdd_on()
1764 	struct drm_i915_private *dev_priv = dev->dev_private;  in edp_panel_vdd_off_sync()  local
1772 	lockdep_assert_held(&dev_priv->pps_mutex);  in edp_panel_vdd_off_sync()
1799 	intel_display_power_put(dev_priv, power_domain);  in edp_panel_vdd_off_sync()
1833 	struct drm_i915_private *dev_priv =  in edp_panel_vdd_off()  local
1836 	lockdep_assert_held(&dev_priv->pps_mutex);  in edp_panel_vdd_off()
1855 	struct drm_i915_private *dev_priv = dev->dev_private;  in edp_panel_on()  local
1859 	lockdep_assert_held(&dev_priv->pps_mutex);  in edp_panel_on()
1916 	struct drm_i915_private *dev_priv = dev->dev_private;  in edp_panel_off()  local
1921 	lockdep_assert_held(&dev_priv->pps_mutex);  in edp_panel_off()
1950 	intel_display_power_put(dev_priv, power_domain);  in edp_panel_off()
1968 	struct drm_i915_private *dev_priv = dev->dev_private;  in _intel_edp_backlight_on()  local
2009 	struct drm_i915_private *dev_priv = dev->dev_private;  in _intel_edp_backlight_off()  local
2075 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_edp_pll_on()  local
2078 	assert_pipe_disabled(dev_priv,  in ironlake_edp_pll_on()
2101 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_edp_pll_off()  local
2104 	assert_pipe_disabled(dev_priv,  in ironlake_edp_pll_off()
2158 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_get_hw_state()  local
2163 	if (!intel_display_power_is_enabled(dev_priv, power_domain))  in intel_dp_get_hw_state()
2196 		for_each_pipe(dev_priv, i) {  in intel_dp_get_hw_state()
2217 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_get_config()  local
2269 	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)  in intel_dp_get_config()
2274 	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&  in intel_dp_get_config()
2275 	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {  in intel_dp_get_config()
2290 			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);  in intel_dp_get_config()
2291 		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;  in intel_dp_get_config()
2341 	struct drm_i915_private *dev_priv = dev->dev_private;  in chv_post_disable_dp()  local
2350 	mutex_lock(&dev_priv->dpio_lock);  in chv_post_disable_dp()
2353 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_post_disable_dp()
2355 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_post_disable_dp()
2357 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_post_disable_dp()
2359 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_post_disable_dp()
2361 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_post_disable_dp()
2363 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_post_disable_dp()
2365 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_post_disable_dp()
2367 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_post_disable_dp()
2369 	mutex_unlock(&dev_priv->dpio_lock);  in chv_post_disable_dp()
2379 	struct drm_i915_private *dev_priv = dev->dev_private;  in _intel_dp_set_link_train()  local
2458 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_enable_port()  local
2483 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_enable_dp()  local
2504 		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));  in intel_enable_dp()
2551 	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;  in vlv_detach_power_sequencer()  local
2577 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_steal_power_sequencer()  local
2580 	lockdep_assert_held(&dev_priv->pps_mutex);  in vlv_steal_power_sequencer()
2616 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_init_panel_power_sequencer()  local
2619 	lockdep_assert_held(&dev_priv->pps_mutex);  in vlv_init_panel_power_sequencer()
2657 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_pre_enable_dp()  local
2663 	mutex_lock(&dev_priv->dpio_lock);  in vlv_pre_enable_dp()
2665 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));  in vlv_pre_enable_dp()
2672 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);  in vlv_pre_enable_dp()
2673 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);  in vlv_pre_enable_dp()
2674 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);  in vlv_pre_enable_dp()
2676 	mutex_unlock(&dev_priv->dpio_lock);  in vlv_pre_enable_dp()
2685 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_dp_pre_pll_enable()  local
2694 	mutex_lock(&dev_priv->dpio_lock);  in vlv_dp_pre_pll_enable()
2695 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),  in vlv_dp_pre_pll_enable()
2698 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),  in vlv_dp_pre_pll_enable()
2705 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);  in vlv_dp_pre_pll_enable()
2706 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);  in vlv_dp_pre_pll_enable()
2707 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);  in vlv_dp_pre_pll_enable()
2708 	mutex_unlock(&dev_priv->dpio_lock);  in vlv_dp_pre_pll_enable()
2716 	struct drm_i915_private *dev_priv = dev->dev_private;  in chv_pre_enable_dp()  local
2724 	mutex_lock(&dev_priv->dpio_lock);  in chv_pre_enable_dp()
2727 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_pre_enable_dp()
2729 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_pre_enable_dp()
2731 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_pre_enable_dp()
2733 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_pre_enable_dp()
2736 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_pre_enable_dp()
2738 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_pre_enable_dp()
2740 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_pre_enable_dp()
2742 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_pre_enable_dp()
2744 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_pre_enable_dp()
2746 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_pre_enable_dp()
2748 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_pre_enable_dp()
2750 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_pre_enable_dp()
2756 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),  in chv_pre_enable_dp()
2763 	mutex_unlock(&dev_priv->dpio_lock);  in chv_pre_enable_dp()
2772 	struct drm_i915_private *dev_priv = dev->dev_private;  in chv_dp_pre_pll_enable()  local
2781 	mutex_lock(&dev_priv->dpio_lock);  in chv_dp_pre_pll_enable()
2785 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_dp_pre_pll_enable()
2791 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_dp_pre_pll_enable()
2793 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_dp_pre_pll_enable()
2799 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_dp_pre_pll_enable()
2803 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));  in chv_dp_pre_pll_enable()
2809 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);  in chv_dp_pre_pll_enable()
2811 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));  in chv_dp_pre_pll_enable()
2817 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);  in chv_dp_pre_pll_enable()
2824 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));  in chv_dp_pre_pll_enable()
2829 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);  in chv_dp_pre_pll_enable()
2831 	mutex_unlock(&dev_priv->dpio_lock);  in chv_dp_pre_pll_enable()
2883 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_voltage_max()  local
2887 		if (dev_priv->vbt.edp_low_vswing && port == PORT_A)  in intel_dp_voltage_max()
2971 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_vlv_signal_levels()  local
3054 	mutex_lock(&dev_priv->dpio_lock);  in intel_vlv_signal_levels()
3055 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);  in intel_vlv_signal_levels()
3056 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);  in intel_vlv_signal_levels()
3057 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),  in intel_vlv_signal_levels()
3059 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);  in intel_vlv_signal_levels()
3060 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);  in intel_vlv_signal_levels()
3061 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);  in intel_vlv_signal_levels()
3062 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);  in intel_vlv_signal_levels()
3063 	mutex_unlock(&dev_priv->dpio_lock);  in intel_vlv_signal_levels()
3071 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_chv_signal_levels()  local
3150 	mutex_lock(&dev_priv->dpio_lock);  in intel_chv_signal_levels()
3153 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in intel_chv_signal_levels()
3157 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in intel_chv_signal_levels()
3159 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in intel_chv_signal_levels()
3163 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in intel_chv_signal_levels()
3165 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));  in intel_chv_signal_levels()
3168 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);  in intel_chv_signal_levels()
3170 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));  in intel_chv_signal_levels()
3173 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);  in intel_chv_signal_levels()
3177 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));  in intel_chv_signal_levels()
3180 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);  in intel_chv_signal_levels()
3185 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in intel_chv_signal_levels()
3188 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in intel_chv_signal_levels()
3193 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in intel_chv_signal_levels()
3195 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in intel_chv_signal_levels()
3210 			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in intel_chv_signal_levels()
3212 			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in intel_chv_signal_levels()
3216 			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in intel_chv_signal_levels()
3219 			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in intel_chv_signal_levels()
3224 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in intel_chv_signal_levels()
3226 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in intel_chv_signal_levels()
3228 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in intel_chv_signal_levels()
3230 	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in intel_chv_signal_levels()
3233 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);  in intel_chv_signal_levels()
3235 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);  in intel_chv_signal_levels()
3237 	mutex_unlock(&dev_priv->dpio_lock);  in intel_chv_signal_levels()
3450 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_set_link_train()  local
3491 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_update_link_train()  local
3510 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_set_idle_link_train()  local
3723 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_link_down()  local
3772 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_get_dpcd()  local
3791 			dev_priv->psr.sink_support = true;  in intel_dp_get_dpcd()
4158 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_dp_detect()  local
4161 	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))  in ironlake_dp_detect()
4170 	struct drm_i915_private *dev_priv = dev->dev_private;  in g4x_digital_port_connected()  local
4424 	struct drm_i915_private *dev_priv = connector->dev->dev_private;  in intel_dp_set_property()  local
4434 	if (property == dev_priv->force_audio_property) {  in intel_dp_set_property()
4455 	if (property == dev_priv->broadcast_rgb_property) {  in intel_dp_set_property()
4573 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_edp_panel_vdd_sanitize()  local
4576 	lockdep_assert_held(&dev_priv->pps_mutex);  in intel_edp_panel_vdd_sanitize()
4589 	intel_display_power_get(dev_priv, power_domain);  in intel_edp_panel_vdd_sanitize()
4652 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_hpd_pulse()  local
4676 	intel_display_power_get(dev_priv, power_domain);  in intel_dp_hpd_pulse()
4681 			if (!ibx_digital_port_connected(dev_priv, intel_dig_port))  in intel_dp_hpd_pulse()
4724 	intel_display_power_put(dev_priv, power_domain);  in intel_dp_hpd_pulse()
4751 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_is_edp()  local
4763 	if (!dev_priv->vbt.child_dev_num)  in intel_dp_is_edp()
4766 	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {  in intel_dp_is_edp()
4767 		p_child = dev_priv->vbt.child_dev + i;  in intel_dp_is_edp()
4807 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_init_panel_power_sequencer()  local
4813 	lockdep_assert_held(&dev_priv->pps_mutex);  in intel_dp_init_panel_power_sequencer()
4861 	vbt = dev_priv->vbt.edp_pps;  in intel_dp_init_panel_power_sequencer()
4910 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_init_panel_power_sequencer_registers()  local
4917 	lockdep_assert_held(&dev_priv->pps_mutex);  in intel_dp_init_panel_power_sequencer_registers()
4986 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_set_drrs_state()  local
4989 	struct intel_dp *intel_dp = dev_priv->drrs.dp;  in intel_dp_set_drrs_state()
5021 	if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {  in intel_dp_set_drrs_state()
5030 	if (index == dev_priv->drrs.refresh_rate_type) {  in intel_dp_set_drrs_state()
5071 	dev_priv->drrs.refresh_rate_type = index;  in intel_dp_set_drrs_state()
5085 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_edp_drrs_enable()  local
5095 	mutex_lock(&dev_priv->drrs.mutex);  in intel_edp_drrs_enable()
5096 	if (WARN_ON(dev_priv->drrs.dp)) {  in intel_edp_drrs_enable()
5101 	dev_priv->drrs.busy_frontbuffer_bits = 0;  in intel_edp_drrs_enable()
5103 	dev_priv->drrs.dp = intel_dp;  in intel_edp_drrs_enable()
5106 	mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_enable()
5117 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_edp_drrs_disable()  local
5125 	mutex_lock(&dev_priv->drrs.mutex);  in intel_edp_drrs_disable()
5126 	if (!dev_priv->drrs.dp) {  in intel_edp_drrs_disable()
5127 		mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_disable()
5131 	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)  in intel_edp_drrs_disable()
5132 		intel_dp_set_drrs_state(dev_priv->dev,  in intel_edp_drrs_disable()
5136 	dev_priv->drrs.dp = NULL;  in intel_edp_drrs_disable()
5137 	mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_disable()
5139 	cancel_delayed_work_sync(&dev_priv->drrs.work);  in intel_edp_drrs_disable()
5144 	struct drm_i915_private *dev_priv =  in intel_edp_drrs_downclock_work()  local
5145 		container_of(work, typeof(*dev_priv), drrs.work.work);  in intel_edp_drrs_downclock_work()
5148 	mutex_lock(&dev_priv->drrs.mutex);  in intel_edp_drrs_downclock_work()
5150 	intel_dp = dev_priv->drrs.dp;  in intel_edp_drrs_downclock_work()
5160 	if (dev_priv->drrs.busy_frontbuffer_bits)  in intel_edp_drrs_downclock_work()
5163 	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)  in intel_edp_drrs_downclock_work()
5164 		intel_dp_set_drrs_state(dev_priv->dev,  in intel_edp_drrs_downclock_work()
5169 	mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_downclock_work()
5186 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_edp_drrs_invalidate()  local
5190 	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)  in intel_edp_drrs_invalidate()
5193 	cancel_delayed_work(&dev_priv->drrs.work);  in intel_edp_drrs_invalidate()
5195 	mutex_lock(&dev_priv->drrs.mutex);  in intel_edp_drrs_invalidate()
5196 	if (!dev_priv->drrs.dp) {  in intel_edp_drrs_invalidate()
5197 		mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_invalidate()
5201 	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;  in intel_edp_drrs_invalidate()
5204 	if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {  in intel_edp_drrs_invalidate()
5205 		intel_dp_set_drrs_state(dev_priv->dev,  in intel_edp_drrs_invalidate()
5206 				dev_priv->drrs.dp->attached_connector->panel.  in intel_edp_drrs_invalidate()
5212 	dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;  in intel_edp_drrs_invalidate()
5213 	mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_invalidate()
5230 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_edp_drrs_flush()  local
5234 	if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)  in intel_edp_drrs_flush()
5237 	cancel_delayed_work(&dev_priv->drrs.work);  in intel_edp_drrs_flush()
5239 	mutex_lock(&dev_priv->drrs.mutex);  in intel_edp_drrs_flush()
5240 	if (!dev_priv->drrs.dp) {  in intel_edp_drrs_flush()
5241 		mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_flush()
5245 	crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;  in intel_edp_drrs_flush()
5247 	dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;  in intel_edp_drrs_flush()
5249 	if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR &&  in intel_edp_drrs_flush()
5250 			!dev_priv->drrs.busy_frontbuffer_bits)  in intel_edp_drrs_flush()
5251 		schedule_delayed_work(&dev_priv->drrs.work,  in intel_edp_drrs_flush()
5253 	mutex_unlock(&dev_priv->drrs.mutex);  in intel_edp_drrs_flush()
5312 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_drrs_init()  local
5315 	INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);  in intel_dp_drrs_init()
5316 	mutex_init(&dev_priv->drrs.mutex);  in intel_dp_drrs_init()
5323 	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {  in intel_dp_drrs_init()
5336 	dev_priv->drrs.type = dev_priv->vbt.drrs_type;  in intel_dp_drrs_init()
5338 	dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;  in intel_dp_drrs_init()
5350 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_edp_init_connector()  local
5370 			dev_priv->no_aux_handshake =  in intel_edp_init_connector()
5411 	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {  in intel_edp_init_connector()
5413 					dev_priv->vbt.lfp_lvds_vbt_mode);  in intel_edp_init_connector()
5458 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_init_connector()  local
5597 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_init()  local
5657 	dev_priv->hpd_irq_port[port] = intel_dig_port;  in intel_dp_init()
5668 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_mst_suspend()  local
5673 		struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];  in intel_dp_mst_suspend()
5688 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_dp_mst_resume()  local
5692 		struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];  in intel_dp_mst_resume()