259 	if (IS_VALLEYVIEW(dev))  in intel_hrawclk()
534 	if (WARN_ON(!IS_VALLEYVIEW(dev)))  in vlv_power_sequencer_reset()
595 	if (IS_VALLEYVIEW(dev)) {  in edp_notify_handler()
621 	if (IS_VALLEYVIEW(dev) &&  in edp_have_panel_power()
635 	if (IS_VALLEYVIEW(dev) &&  in edp_have_panel_vdd()
1203 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_set_clock()
1556 	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {  in intel_dp_prepare()
1568 		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))  in intel_dp_prepare()
2171 	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {  in intel_dp_get_hw_state()
2251 	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&  in intel_dp_get_config()
2492 	if (IS_VALLEYVIEW(dev))  in intel_enable_dp()
2503 	if (IS_VALLEYVIEW(dev))  in intel_enable_dp()
2890 	} else if (IS_VALLEYVIEW(dev))  in intel_dp_voltage_max()
2931 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_pre_emphasis_max()
3424 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_set_signal_levels()
4173 	if (IS_VALLEYVIEW(dev)) {  in g4x_digital_port_connected()
4609 	if (IS_VALLEYVIEW(encoder->dev))  in intel_dp_encoder_reset()
4951 	if (IS_VALLEYVIEW(dev)) {  in intel_dp_init_panel_power_sequencer_registers()
5058 			if (IS_VALLEYVIEW(dev))  in intel_dp_set_drrs_state()
5063 			if (IS_VALLEYVIEW(dev))  in intel_dp_set_drrs_state()
5419 	if (IS_VALLEYVIEW(dev)) {  in intel_edp_init_connector()
5467 	else if (IS_VALLEYVIEW(dev))  in intel_dp_init_connector()
5499 	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&  in intel_dp_init_connector()
5546 		if (IS_VALLEYVIEW(dev))  in intel_dp_init_connector()
5629 	} else if (IS_VALLEYVIEW(dev)) {  in intel_dp_init()