1032 		if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,  in intel_wait_for_pipe_off()
1037 		if (wait_for(pipe_dsl_stopped(dev, pipe), 100))  in intel_wait_for_pipe_off()
1604 	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))  in vlv_enable_pll()
1651 	if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))  in chv_enable_pll()
1846 	if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))  in vlv_wait_port_ready()
1995 	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))  in ironlake_enable_pch_transcoder()
2026 	if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))  in lpt_enable_pch_transcoder()
2048 	if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))  in ironlake_disable_pch_transcoder()
2068 	if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))  in lpt_disable_pch_transcoder()
4250 	if (wait_for(I915_READ(dslreg) != temp, 5)) {  in cpt_verify_modeset()
4251 		if (wait_for(I915_READ(dslreg) != temp, 5))  in cpt_verify_modeset()
4364 		if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))  in hsw_enable_ips()
4383 		if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))  in hsw_disable_ips()
5049 	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &  in valleyview_set_cdclk()
5068 		if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &  in valleyview_set_cdclk()
5124 	if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &  in cherryview_set_cdclk()
8343 	if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))  in hsw_disable_lcpll()
8351 	if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,  in hsw_disable_lcpll()
8398 	if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))  in hsw_restore_lcpll()