Lines Matching refs:pipe_src_w
2708 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2713 (intel_crtc->config->pipe_src_w - 1)); in i9xx_update_primary_plane()
2771 x += (intel_crtc->config->pipe_src_w - 1); in i9xx_update_primary_plane()
2778 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in i9xx_update_primary_plane()
2871 x += (intel_crtc->config->pipe_src_w - 1); in ironlake_update_primary_plane()
2878 (intel_crtc->config->pipe_src_w - 1) * pixel_size; in ironlake_update_primary_plane()
3025 (intel_crtc->config->pipe_src_w - 1)); in skylake_update_primary_plane()
3233 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; in intel_update_pipe_size()
5852 pipe_config->pipe_src_w &= ~1; in intel_crtc_compute_config()
6653 ((intel_crtc->config->pipe_src_w - 1) << 16) | in intel_set_pipe_timings()
6693 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
6696 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; in intel_get_pipe_timings()
8768 if (x >= intel_crtc->config->pipe_src_w) in intel_crtc_update_cursor()
10525 pipe_config->pipe_src_w, pipe_config->pipe_src_h); in intel_dump_pipe_config()
10701 &pipe_config->pipe_src_w, in intel_modeset_pipe_config()
11073 PIPE_CONF_CHECK_I(pipe_src_w); in intel_pipe_config_compare()