Lines Matching refs:pipe
107 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) in intel_find_encoder() argument
112 return &connector->mst_port->mst_encoders[pipe]->base; in intel_find_encoder()
978 enum pipe pipe) in intel_pipe_to_cpu_transcoder() argument
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_pipe_to_cpu_transcoder()
986 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) in pipe_dsl_stopped() argument
989 u32 reg = PIPEDSL(pipe); in pipe_dsl_stopped()
1026 enum pipe pipe = crtc->pipe; in intel_wait_for_pipe_off() local
1037 if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) in intel_wait_for_pipe_off()
1094 enum pipe pipe, bool state) in assert_pll() argument
1100 reg = DPLL(pipe); in assert_pll()
1156 enum pipe pipe, bool state) in assert_fdi_tx() argument
1162 pipe); in assert_fdi_tx()
1170 reg = FDI_TX_CTL(pipe); in assert_fdi_tx()
1182 enum pipe pipe, bool state) in assert_fdi_rx() argument
1188 reg = FDI_RX_CTL(pipe); in assert_fdi_rx()
1199 enum pipe pipe) in assert_fdi_tx_pll_enabled() argument
1212 reg = FDI_TX_CTL(pipe); in assert_fdi_tx_pll_enabled()
1218 enum pipe pipe, bool state) in assert_fdi_rx_pll() argument
1224 reg = FDI_RX_CTL(pipe); in assert_fdi_rx_pll()
1233 enum pipe pipe) in assert_panel_unlocked() argument
1238 enum pipe panel_pipe = PIPE_A; in assert_panel_unlocked()
1256 pp_reg = VLV_PIPE_PP_CONTROL(pipe); in assert_panel_unlocked()
1257 panel_pipe = pipe; in assert_panel_unlocked()
1269 I915_STATE_WARN(panel_pipe == pipe && locked, in assert_panel_unlocked()
1271 pipe_name(pipe)); in assert_panel_unlocked()
1275 enum pipe pipe, bool state) in assert_cursor() argument
1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; in assert_cursor()
1287 pipe_name(pipe), state_string(state), state_string(cur_state)); in assert_cursor()
1293 enum pipe pipe, bool state) in assert_pipe() argument
1299 pipe); in assert_pipe()
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in assert_pipe()
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in assert_pipe()
1317 pipe_name(pipe), state_string(state), state_string(cur_state)); in assert_pipe()
1339 enum pipe pipe) in assert_planes_disabled() argument
1348 reg = DSPCNTR(pipe); in assert_planes_disabled()
1352 plane_name(pipe)); in assert_planes_disabled()
1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, in assert_planes_disabled()
1364 plane_name(i), pipe_name(pipe)); in assert_planes_disabled()
1369 enum pipe pipe) in assert_sprites_disabled() argument
1376 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1377 val = I915_READ(PLANE_CTL(pipe, sprite)); in assert_sprites_disabled()
1380 sprite, pipe_name(pipe)); in assert_sprites_disabled()
1383 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1384 reg = SPCNTR(pipe, sprite); in assert_sprites_disabled()
1388 sprite_name(pipe, sprite), pipe_name(pipe)); in assert_sprites_disabled()
1391 reg = SPRCTL(pipe); in assert_sprites_disabled()
1395 plane_name(pipe), pipe_name(pipe)); in assert_sprites_disabled()
1397 reg = DVSCNTR(pipe); in assert_sprites_disabled()
1401 plane_name(pipe), pipe_name(pipe)); in assert_sprites_disabled()
1425 enum pipe pipe) in assert_pch_transcoder_disabled() argument
1431 reg = PCH_TRANSCONF(pipe); in assert_pch_transcoder_disabled()
1436 pipe_name(pipe)); in assert_pch_transcoder_disabled()
1440 enum pipe pipe, u32 port_sel, u32 val) in dp_pipe_enabled() argument
1446 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); in dp_pipe_enabled()
1451 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) in dp_pipe_enabled()
1454 if ((val & DP_PIPE_MASK) != (pipe << 30)) in dp_pipe_enabled()
1461 enum pipe pipe, u32 val) in hdmi_pipe_enabled() argument
1467 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) in hdmi_pipe_enabled()
1470 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) in hdmi_pipe_enabled()
1473 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) in hdmi_pipe_enabled()
1480 enum pipe pipe, u32 val) in lvds_pipe_enabled() argument
1486 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) in lvds_pipe_enabled()
1489 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) in lvds_pipe_enabled()
1496 enum pipe pipe, u32 val) in adpa_pipe_enabled() argument
1501 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) in adpa_pipe_enabled()
1504 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) in adpa_pipe_enabled()
1511 enum pipe pipe, int reg, u32 port_sel) in assert_pch_dp_disabled() argument
1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), in assert_pch_dp_disabled()
1516 reg, pipe_name(pipe)); in assert_pch_dp_disabled()
1524 enum pipe pipe, int reg) in assert_pch_hdmi_disabled() argument
1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), in assert_pch_hdmi_disabled()
1529 reg, pipe_name(pipe)); in assert_pch_hdmi_disabled()
1537 enum pipe pipe) in assert_pch_ports_disabled() argument
1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); in assert_pch_ports_disabled()
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); in assert_pch_ports_disabled()
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); in assert_pch_ports_disabled()
1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1550 pipe_name(pipe)); in assert_pch_ports_disabled()
1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1556 pipe_name(pipe)); in assert_pch_ports_disabled()
1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); in assert_pch_ports_disabled()
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); in assert_pch_ports_disabled()
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); in assert_pch_ports_disabled()
1588 int reg = DPLL(crtc->pipe); in vlv_enable_pll()
1591 assert_pipe_disabled(dev_priv, crtc->pipe); in vlv_enable_pll()
1598 assert_panel_unlocked(dev_priv, crtc->pipe); in vlv_enable_pll()
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); in vlv_enable_pll()
1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); in vlv_enable_pll()
1608 POSTING_READ(DPLL_MD(crtc->pipe)); in vlv_enable_pll()
1627 int pipe = crtc->pipe; in chv_enable_pll() local
1628 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_enable_pll()
1631 assert_pipe_disabled(dev_priv, crtc->pipe); in chv_enable_pll()
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_enable_pll()
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); in chv_enable_pll()
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll()
1652 DRM_ERROR("PLL %d failed to lock\n", pipe); in chv_enable_pll()
1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1656 POSTING_READ(DPLL_MD(pipe)); in chv_enable_pll()
1677 int reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1680 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_enable_pll()
1687 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1698 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1709 I915_WRITE(DPLL_MD(crtc->pipe), in i9xx_enable_pll()
1745 enum pipe pipe = crtc->pipe; in i9xx_disable_pll() local
1758 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_disable_pll()
1759 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_disable_pll()
1763 assert_pipe_disabled(dev_priv, pipe); in i9xx_disable_pll()
1765 I915_WRITE(DPLL(pipe), 0); in i9xx_disable_pll()
1766 POSTING_READ(DPLL(pipe)); in i9xx_disable_pll()
1769 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in vlv_disable_pll() argument
1774 assert_pipe_disabled(dev_priv, pipe); in vlv_disable_pll()
1780 if (pipe == PIPE_B) in vlv_disable_pll()
1782 I915_WRITE(DPLL(pipe), val); in vlv_disable_pll()
1783 POSTING_READ(DPLL(pipe)); in vlv_disable_pll()
1787 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in chv_disable_pll() argument
1789 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_disable_pll()
1793 assert_pipe_disabled(dev_priv, pipe); in chv_disable_pll()
1797 if (pipe != PIPE_A) in chv_disable_pll()
1799 I915_WRITE(DPLL(pipe), val); in chv_disable_pll()
1800 POSTING_READ(DPLL(pipe)); in chv_disable_pll()
1805 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll()
1807 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); in chv_disable_pll()
1810 if (pipe != PIPE_B) { in chv_disable_pll()
1811 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_disable_pll()
1813 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_disable_pll()
1815 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_disable_pll()
1817 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_disable_pll()
1944 enum pipe pipe) in ironlake_enable_pch_transcoder() argument
1947 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in ironlake_enable_pch_transcoder()
1959 assert_fdi_tx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1960 assert_fdi_rx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1965 reg = TRANS_CHICKEN2(pipe); in ironlake_enable_pch_transcoder()
1971 reg = PCH_TRANSCONF(pipe); in ironlake_enable_pch_transcoder()
1973 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
1996 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); in ironlake_enable_pch_transcoder()
2008 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); in lpt_enable_pch_transcoder()
2031 enum pipe pipe) in ironlake_disable_pch_transcoder() argument
2037 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2038 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2041 assert_pch_ports_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2043 reg = PCH_TRANSCONF(pipe); in ironlake_disable_pch_transcoder()
2049 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); in ironlake_disable_pch_transcoder()
2053 reg = TRANS_CHICKEN2(pipe); in ironlake_disable_pch_transcoder()
2088 enum pipe pipe = crtc->pipe; in intel_enable_pipe() local
2090 pipe); in intel_enable_pipe()
2091 enum pipe pch_transcoder; in intel_enable_pipe()
2095 assert_planes_disabled(dev_priv, pipe); in intel_enable_pipe()
2096 assert_cursor_disabled(dev_priv, pipe); in intel_enable_pipe()
2097 assert_sprites_disabled(dev_priv, pipe); in intel_enable_pipe()
2102 pch_transcoder = pipe; in intel_enable_pipe()
2113 assert_pll_enabled(dev_priv, pipe); in intel_enable_pipe()
2119 (enum pipe) cpu_transcoder); in intel_enable_pipe()
2127 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in intel_enable_pipe()
2128 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); in intel_enable_pipe()
2150 enum pipe pipe = crtc->pipe; in intel_disable_pipe() local
2158 assert_planes_disabled(dev_priv, pipe); in intel_disable_pipe()
2159 assert_cursor_disabled(dev_priv, pipe); in intel_disable_pipe()
2160 assert_sprites_disabled(dev_priv, pipe); in intel_disable_pipe()
2175 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && in intel_disable_pipe()
2176 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in intel_disable_pipe()
2213 assert_pipe_enabled(dev_priv, intel_crtc->pipe); in intel_enable_primary_hw_plane()
2229 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_enable_primary_hw_plane()
2662 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); in intel_find_initial_plane_obj()
2700 if (intel_crtc->pipe == PIPE_B) in i9xx_update_primary_plane()
2949 int pipe = intel_crtc->pipe; in skylake_update_primary_plane() local
2954 I915_WRITE(PLANE_CTL(pipe, 0), 0); in skylake_update_primary_plane()
2955 I915_WRITE(PLANE_SURF(pipe, 0), 0); in skylake_update_primary_plane()
2956 POSTING_READ(PLANE_CTL(pipe, 0)); in skylake_update_primary_plane()
3020 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); in skylake_update_primary_plane()
3021 I915_WRITE(PLANE_POS(pipe, 0), 0); in skylake_update_primary_plane()
3022 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); in skylake_update_primary_plane()
3023 I915_WRITE(PLANE_SIZE(pipe, 0), in skylake_update_primary_plane()
3026 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div); in skylake_update_primary_plane()
3027 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); in skylake_update_primary_plane()
3029 POSTING_READ(PLANE_SURF(pipe, 0)); in skylake_update_primary_plane()
3223 I915_WRITE(PIPESRC(crtc->pipe), in intel_update_pipe_size()
3229 I915_WRITE(PF_CTL(crtc->pipe), 0); in intel_update_pipe_size()
3230 I915_WRITE(PF_WIN_POS(crtc->pipe), 0); in intel_update_pipe_size()
3231 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); in intel_update_pipe_size()
3242 int pipe = intel_crtc->pipe; in intel_fdi_normal_train() local
3246 reg = FDI_TX_CTL(pipe); in intel_fdi_normal_train()
3257 reg = FDI_RX_CTL(pipe); in intel_fdi_normal_train()
3284 int pipe = intel_crtc->pipe; in ironlake_fdi_link_train() local
3288 assert_pipe_enabled(dev_priv, pipe); in ironlake_fdi_link_train()
3292 reg = FDI_RX_IMR(pipe); in ironlake_fdi_link_train()
3301 reg = FDI_TX_CTL(pipe); in ironlake_fdi_link_train()
3309 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
3319 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); in ironlake_fdi_link_train()
3320 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | in ironlake_fdi_link_train()
3323 reg = FDI_RX_IIR(pipe); in ironlake_fdi_link_train()
3338 reg = FDI_TX_CTL(pipe); in ironlake_fdi_link_train()
3344 reg = FDI_RX_CTL(pipe); in ironlake_fdi_link_train()
3353 reg = FDI_RX_IIR(pipe); in ironlake_fdi_link_train()
3384 int pipe = intel_crtc->pipe; in gen6_fdi_link_train() local
3389 reg = FDI_RX_IMR(pipe); in gen6_fdi_link_train()
3399 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3410 I915_WRITE(FDI_RX_MISC(pipe), in gen6_fdi_link_train()
3413 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
3428 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3438 reg = FDI_RX_IIR(pipe); in gen6_fdi_link_train()
3455 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3466 reg = FDI_RX_CTL(pipe); in gen6_fdi_link_train()
3481 reg = FDI_TX_CTL(pipe); in gen6_fdi_link_train()
3491 reg = FDI_RX_IIR(pipe); in gen6_fdi_link_train()
3516 int pipe = intel_crtc->pipe; in ivb_manual_fdi_link_train() local
3521 reg = FDI_RX_IMR(pipe); in ivb_manual_fdi_link_train()
3531 I915_READ(FDI_RX_IIR(pipe))); in ivb_manual_fdi_link_train()
3536 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
3542 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
3550 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
3560 I915_WRITE(FDI_RX_MISC(pipe), in ivb_manual_fdi_link_train()
3563 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
3573 reg = FDI_RX_IIR(pipe); in ivb_manual_fdi_link_train()
3592 reg = FDI_TX_CTL(pipe); in ivb_manual_fdi_link_train()
3598 reg = FDI_RX_CTL(pipe); in ivb_manual_fdi_link_train()
3608 reg = FDI_RX_IIR(pipe); in ivb_manual_fdi_link_train()
3633 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_enable() local
3638 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_enable()
3642 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
3656 reg = FDI_TX_CTL(pipe); in ironlake_fdi_pll_enable()
3670 int pipe = intel_crtc->pipe; in ironlake_fdi_pll_disable() local
3674 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_disable()
3679 reg = FDI_TX_CTL(pipe); in ironlake_fdi_pll_disable()
3686 reg = FDI_RX_CTL(pipe); in ironlake_fdi_pll_disable()
3700 int pipe = intel_crtc->pipe; in ironlake_fdi_disable() local
3704 reg = FDI_TX_CTL(pipe); in ironlake_fdi_disable()
3709 reg = FDI_RX_CTL(pipe); in ironlake_fdi_disable()
3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3720 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); in ironlake_fdi_disable()
3723 reg = FDI_TX_CTL(pipe); in ironlake_fdi_disable()
3729 reg = FDI_RX_CTL(pipe); in ironlake_fdi_disable()
3740 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3763 intel_wait_for_vblank(dev, crtc->pipe); in intel_has_pending_fb_unpin()
3782 intel_crtc->pipe, in page_flip_completed()
3910 enum pipe pch_transcoder) in ironlake_pch_transcoder_set_timings()
3958 switch (intel_crtc->pipe) { in ivybridge_update_fdi_bc_bifurcation()
3990 int pipe = intel_crtc->pipe; in ironlake_pch_enable() local
3993 assert_pch_transcoder_disabled(dev_priv, pipe); in ironlake_pch_enable()
4000 I915_WRITE(FDI_RX_TUSIZE1(pipe), in ironlake_pch_enable()
4001 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); in ironlake_pch_enable()
4012 temp |= TRANS_DPLL_ENABLE(pipe); in ironlake_pch_enable()
4013 sel = TRANS_DPLLB_SEL(pipe); in ironlake_pch_enable()
4031 assert_panel_unlocked(dev_priv, pipe); in ironlake_pch_enable()
4032 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); in ironlake_pch_enable()
4038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
4039 reg = TRANS_DP_CTL(pipe); in ironlake_pch_enable()
4070 ironlake_enable_pch_transcoder(dev_priv, pipe); in ironlake_pch_enable()
4097 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { in intel_put_shared_dpll()
4102 pll->config.crtc_mask &= ~(1 << crtc->pipe); in intel_put_shared_dpll()
4120 i = (enum intel_dpll_id) crtc->pipe; in intel_get_shared_dpll()
4167 pipe_name(crtc->pipe)); in intel_get_shared_dpll()
4169 pll->new_config->crtc_mask |= 1 << crtc->pipe; in intel_get_shared_dpll()
4242 static void cpt_verify_modeset(struct drm_device *dev, int pipe) in cpt_verify_modeset() argument
4245 int dslreg = PIPEDSL(pipe); in cpt_verify_modeset()
4252 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); in cpt_verify_modeset()
4260 int pipe = crtc->pipe; in skylake_pfit_enable() local
4263 I915_WRITE(PS_CTL(pipe), PS_ENABLE); in skylake_pfit_enable()
4264 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos); in skylake_pfit_enable()
4265 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size); in skylake_pfit_enable()
4273 int pipe = crtc->pipe; in ironlake_pfit_enable() local
4281 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | in ironlake_pfit_enable()
4282 PF_PIPE_SEL_IVB(pipe)); in ironlake_pfit_enable()
4284 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); in ironlake_pfit_enable()
4285 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); in ironlake_pfit_enable()
4286 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); in ironlake_pfit_enable()
4293 enum pipe pipe = to_intel_crtc(crtc)->pipe; in intel_enable_sprite_planes() local
4299 if (intel_plane->pipe == pipe) in intel_enable_sprite_planes()
4325 enum pipe pipe = to_intel_crtc(crtc)->pipe; in intel_disable_sprite_planes() local
4331 if (plane->fb && intel_plane->pipe == pipe) in intel_disable_sprite_planes()
4345 intel_wait_for_vblank(dev, crtc->pipe); in hsw_enable_ips()
4391 intel_wait_for_vblank(dev, crtc->pipe); in hsw_disable_ips()
4400 enum pipe pipe = intel_crtc->pipe; in intel_crtc_load_lut() local
4401 int palreg = PALETTE(pipe); in intel_crtc_load_lut()
4413 assert_pll_enabled(dev_priv, pipe); in intel_crtc_load_lut()
4418 palreg = LGC_PALETTE(pipe); in intel_crtc_load_lut()
4424 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == in intel_crtc_load_lut()
4463 int pipe = intel_crtc->pipe; in intel_crtc_enable_planes() local
4481 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); in intel_crtc_enable_planes()
4489 int pipe = intel_crtc->pipe; in intel_crtc_disable_planes() local
4508 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); in intel_crtc_disable_planes()
4517 int pipe = intel_crtc->pipe; in ironlake_crtc_enable() local
4541 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4542 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4554 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4555 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4579 cpt_verify_modeset(dev, intel_crtc->pipe); in ironlake_crtc_enable()
4587 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
4615 intel_wait_for_vblank(dev, other_active_crtc->pipe); in haswell_mode_set_planes_workaround()
4616 intel_wait_for_vblank(dev, other_active_crtc->pipe); in haswell_mode_set_planes_workaround()
4625 int pipe = intel_crtc->pipe; in haswell_crtc_enable() local
4656 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in haswell_crtc_enable()
4710 int pipe = crtc->pipe; in skylake_pfit_disable() local
4715 I915_WRITE(PS_CTL(pipe), 0); in skylake_pfit_disable()
4716 I915_WRITE(PS_WIN_POS(pipe), 0); in skylake_pfit_disable()
4717 I915_WRITE(PS_WIN_SZ(pipe), 0); in skylake_pfit_disable()
4725 int pipe = crtc->pipe; in ironlake_pfit_disable() local
4730 I915_WRITE(PF_CTL(pipe), 0); in ironlake_pfit_disable()
4731 I915_WRITE(PF_WIN_POS(pipe), 0); in ironlake_pfit_disable()
4732 I915_WRITE(PF_WIN_SZ(pipe), 0); in ironlake_pfit_disable()
4742 int pipe = intel_crtc->pipe; in ironlake_crtc_disable() local
4757 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); in ironlake_crtc_disable()
4770 ironlake_disable_pch_transcoder(dev_priv, pipe); in ironlake_crtc_disable()
4774 reg = TRANS_DP_CTL(pipe); in ironlake_crtc_disable()
4783 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); in ironlake_crtc_disable()
4880 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_enable()
4887 I915_WRITE(BCLRPAT(crtc->pipe), 0); in i9xx_pfit_enable()
4943 enum pipe pipe = intel_crtc->pipe; in get_crtc_power_domains() local
4947 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); in get_crtc_power_domains()
4949 mask = BIT(POWER_DOMAIN_PIPE(pipe)); in get_crtc_power_domains()
4953 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); in get_crtc_power_domains()
4978 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); in modeset_update_crtc_power_domains()
4980 for_each_power_domain(domain, pipe_domains[crtc->pipe]) in modeset_update_crtc_power_domains()
4993 crtc->enabled_power_domains = pipe_domains[crtc->pipe]; in modeset_update_crtc_power_domains()
5194 *prepare_pipes |= (1 << intel_crtc->pipe); in valleyview_modeset_global_pipes()
5269 int pipe = intel_crtc->pipe; in valleyview_crtc_enable() local
5291 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { in valleyview_crtc_enable()
5294 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); in valleyview_crtc_enable()
5295 I915_WRITE(CHV_CANVAS(pipe), 0); in valleyview_crtc_enable()
5302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in valleyview_crtc_enable()
5343 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); in i9xx_set_pll_dividers()
5344 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); in i9xx_set_pll_dividers()
5353 int pipe = intel_crtc->pipe; in i9xx_crtc_enable() local
5372 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in i9xx_crtc_enable()
5403 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in i9xx_crtc_enable()
5417 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_disable()
5430 int pipe = intel_crtc->pipe; in i9xx_crtc_disable() local
5442 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in i9xx_crtc_disable()
5462 intel_wait_for_vblank(dev, pipe); in i9xx_crtc_disable()
5480 chv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
5482 vlv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
5488 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in i9xx_crtc_disable()
5606 enum pipe pipe; in intel_connector_check_state() local
5621 encoder_enabled = encoder->get_hw_state(encoder, &pipe); in intel_connector_check_state()
5631 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, in intel_connector_check_state()
5690 enum pipe pipe = 0; in intel_connector_get_hw_state() local
5693 return encoder->get_hw_state(encoder, &pipe); in intel_connector_get_hw_state()
5696 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe) in pipe_required_fdi_lanes() argument
5699 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); in pipe_required_fdi_lanes()
5708 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, in ironlake_check_fdi_lanes() argument
5712 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
5715 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
5733 switch (pipe) { in ironlake_check_fdi_lanes()
5740 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
5747 pipe_name(pipe), pipe_config->fdi_lanes); in ironlake_check_fdi_lanes()
5790 intel_crtc->pipe, pipe_config); in ironlake_fdi_compute_config()
5834 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && in intel_crtc_compute_config()
6092 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe in vlv_pllb_recal_opamp() argument
6093 pipe) in vlv_pllb_recal_opamp()
6101 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
6104 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
6106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
6109 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
6111 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
6113 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
6115 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
6118 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
6126 int pipe = crtc->pipe; in intel_pch_transcoder_set_m_n() local
6128 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); in intel_pch_transcoder_set_m_n()
6129 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); in intel_pch_transcoder_set_m_n()
6130 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); in intel_pch_transcoder_set_m_n()
6131 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); in intel_pch_transcoder_set_m_n()
6140 int pipe = crtc->pipe; in intel_cpu_transcoder_set_m_n() local
6161 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); in intel_cpu_transcoder_set_m_n()
6162 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); in intel_cpu_transcoder_set_m_n()
6163 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); in intel_cpu_transcoder_set_m_n()
6164 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); in intel_cpu_transcoder_set_m_n()
6206 if (crtc->pipe == PIPE_B) in vlv_update_pll()
6221 int pipe = crtc->pipe; in vlv_prepare_pll() local
6237 if (pipe == PIPE_B) in vlv_prepare_pll()
6238 vlv_pllb_recal_opamp(dev_priv, pipe); in vlv_prepare_pll()
6241 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); in vlv_prepare_pll()
6244 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
6246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); in vlv_prepare_pll()
6249 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); in vlv_prepare_pll()
6263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
6266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
6272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
6275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
6280 if (pipe == PIPE_A) in vlv_prepare_pll()
6281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6288 if (pipe == PIPE_A) in vlv_prepare_pll()
6289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6296 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
6301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); in vlv_prepare_pll()
6303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); in vlv_prepare_pll()
6313 if (crtc->pipe != PIPE_A) in chv_update_pll()
6325 int pipe = crtc->pipe; in chv_prepare_pll() local
6326 int dpll_reg = DPLL(crtc->pipe); in chv_prepare_pll()
6327 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_prepare_pll()
6352 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), in chv_prepare_pll()
6359 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); in chv_prepare_pll()
6362 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), in chv_prepare_pll()
6368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); in chv_prepare_pll()
6371 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll()
6376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); in chv_prepare_pll()
6379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll()
6385 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); in chv_prepare_pll()
6410 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); in chv_prepare_pll()
6412 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); in chv_prepare_pll()
6415 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); in chv_prepare_pll()
6418 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), in chv_prepare_pll()
6419 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | in chv_prepare_pll()
6435 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, in vlv_force_pll_on() argument
6439 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); in vlv_force_pll_on()
6465 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) in vlv_force_pll_off() argument
6468 chv_disable_pll(to_i915(dev), pipe); in vlv_force_pll_off()
6470 vlv_disable_pll(to_i915(dev), pipe); in vlv_force_pll_off()
6592 enum pipe pipe = intel_crtc->pipe; in intel_set_pipe_timings() local
6646 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
6647 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); in intel_set_pipe_timings()
6652 I915_WRITE(PIPESRC(pipe), in intel_set_pipe_timings()
6691 tmp = I915_READ(PIPESRC(crtc->pipe)); in intel_get_pipe_timings()
6726 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_set_pipeconf()
6727 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_set_pipeconf()
6728 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; in i9xx_set_pipeconf()
6777 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); in i9xx_set_pipeconf()
6778 POSTING_READ(PIPECONF(intel_crtc->pipe)); in i9xx_set_pipeconf()
6895 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
6898 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) in i9xx_get_pfit_config()
6914 int pipe = pipe_config->cpu_transcoder; in vlv_crtc_clock_get() local
6924 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get()
6946 int pipe = crtc->pipe, plane = crtc->plane; in i9xx_get_initial_plane_config() local
6987 val = I915_READ(PIPESRC(pipe)); in i9xx_get_initial_plane_config()
6991 val = I915_READ(DSPSTRIDE(pipe)); in i9xx_get_initial_plane_config()
7001 pipe_name(pipe), plane, fb->width, fb->height, in i9xx_get_initial_plane_config()
7013 int pipe = pipe_config->cpu_transcoder; in chv_crtc_clock_get() local
7014 enum dpio_channel port = vlv_pipe_to_channel(pipe); in chv_crtc_clock_get()
7020 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); in chv_crtc_clock_get()
7021 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); in chv_crtc_clock_get()
7022 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); in chv_crtc_clock_get()
7023 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); in chv_crtc_clock_get()
7046 POWER_DOMAIN_PIPE(crtc->pipe))) in i9xx_get_pipe_config()
7049 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in i9xx_get_pipe_config()
7052 tmp = I915_READ(PIPECONF(crtc->pipe)); in i9xx_get_pipe_config()
7083 tmp = I915_READ(DPLL_MD(crtc->pipe)); in i9xx_get_pipe_config()
7089 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7099 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7109 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); in i9xx_get_pipe_config()
7110 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); in i9xx_get_pipe_config()
7522 int pipe = intel_crtc->pipe; in ironlake_set_pipeconf() local
7556 I915_WRITE(PIPECONF(pipe), val); in ironlake_set_pipeconf()
7557 POSTING_READ(PIPECONF(pipe)); in ironlake_set_pipeconf()
7572 int pipe = intel_crtc->pipe; in intel_set_pipe_csc() local
7590 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); in intel_set_pipe_csc()
7591 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); in intel_set_pipe_csc()
7593 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); in intel_set_pipe_csc()
7594 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); in intel_set_pipe_csc()
7596 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); in intel_set_pipe_csc()
7597 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); in intel_set_pipe_csc()
7599 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); in intel_set_pipe_csc()
7600 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); in intel_set_pipe_csc()
7601 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); in intel_set_pipe_csc()
7609 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); in intel_set_pipe_csc()
7610 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); in intel_set_pipe_csc()
7611 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); in intel_set_pipe_csc()
7613 I915_WRITE(PIPE_CSC_MODE(pipe), 0); in intel_set_pipe_csc()
7620 I915_WRITE(PIPE_CSC_MODE(pipe), mode); in intel_set_pipe_csc()
7629 enum pipe pipe = intel_crtc->pipe; in haswell_set_pipeconf() local
7646 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); in haswell_set_pipeconf()
7647 POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); in haswell_set_pipeconf()
7673 I915_WRITE(PIPEMISC(pipe), val); in haswell_set_pipeconf()
7887 pipe_name(crtc->pipe)); in ironlake_crtc_compute_clock()
7905 enum pipe pipe = crtc->pipe; in intel_pch_transcoder_get_m_n() local
7907 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); in intel_pch_transcoder_get_m_n()
7908 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); in intel_pch_transcoder_get_m_n()
7909 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
7911 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); in intel_pch_transcoder_get_m_n()
7912 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) in intel_pch_transcoder_get_m_n()
7923 enum pipe pipe = crtc->pipe; in intel_cpu_transcoder_get_m_n() local
7948 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
7949 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
7950 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
7952 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); in intel_cpu_transcoder_get_m_n()
7953 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) in intel_cpu_transcoder_get_m_n()
7983 tmp = I915_READ(PS_CTL(crtc->pipe)); in skylake_get_pfit_config()
7987 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); in skylake_get_pfit_config()
7988 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); in skylake_get_pfit_config()
7999 int pipe = crtc->pipe; in skylake_get_initial_plane_config() local
8013 val = I915_READ(PLANE_CTL(pipe, 0)); in skylake_get_initial_plane_config()
8044 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; in skylake_get_initial_plane_config()
8047 offset = I915_READ(PLANE_OFFSET(pipe, 0)); in skylake_get_initial_plane_config()
8049 val = I915_READ(PLANE_SIZE(pipe, 0)); in skylake_get_initial_plane_config()
8053 val = I915_READ(PLANE_STRIDE(pipe, 0)); in skylake_get_initial_plane_config()
8065 pipe_name(pipe), fb->width, fb->height, in skylake_get_initial_plane_config()
8083 tmp = I915_READ(PF_CTL(crtc->pipe)); in ironlake_get_pfit_config()
8087 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); in ironlake_get_pfit_config()
8088 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); in ironlake_get_pfit_config()
8095 PF_PIPE_SEL_IVB(crtc->pipe)); in ironlake_get_pfit_config()
8107 int pipe = crtc->pipe; in ironlake_get_initial_plane_config() local
8113 val = I915_READ(DSPCNTR(pipe)); in ironlake_get_initial_plane_config()
8137 base = I915_READ(DSPSURF(pipe)) & 0xfffff000; in ironlake_get_initial_plane_config()
8139 offset = I915_READ(DSPOFFSET(pipe)); in ironlake_get_initial_plane_config()
8142 offset = I915_READ(DSPTILEOFF(pipe)); in ironlake_get_initial_plane_config()
8144 offset = I915_READ(DSPLINOFF(pipe)); in ironlake_get_initial_plane_config()
8148 val = I915_READ(PIPESRC(pipe)); in ironlake_get_initial_plane_config()
8152 val = I915_READ(DSPSTRIDE(pipe)); in ironlake_get_initial_plane_config()
8162 pipe_name(pipe), fb->width, fb->height, in ironlake_get_initial_plane_config()
8177 POWER_DOMAIN_PIPE(crtc->pipe))) in ironlake_get_pipe_config()
8180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in ironlake_get_pipe_config()
8183 tmp = I915_READ(PIPECONF(crtc->pipe)); in ironlake_get_pipe_config()
8207 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { in ironlake_get_pipe_config()
8212 tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); in ironlake_get_pipe_config()
8220 (enum intel_dpll_id) crtc->pipe; in ironlake_get_pipe_config()
8223 if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) in ironlake_get_pipe_config()
8258 pipe_name(crtc->pipe)); in assert_can_disable_lcpll()
8582 POWER_DOMAIN_PIPE(crtc->pipe))) in haswell_get_pipe_config()
8585 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; in haswell_get_pipe_config()
8590 enum pipe trans_edp_pipe; in haswell_get_pipe_config()
8606 if (trans_edp_pipe == crtc->pipe) in haswell_get_pipe_config()
8622 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); in haswell_get_pipe_config()
8711 int pipe = intel_crtc->pipe; in i9xx_update_cursor() local
8731 cntl |= pipe << 28; /* Connect to correct pipe */ in i9xx_update_cursor()
8741 I915_WRITE(CURCNTR(pipe), cntl); in i9xx_update_cursor()
8742 POSTING_READ(CURCNTR(pipe)); in i9xx_update_cursor()
8747 I915_WRITE(CURBASE(pipe), base); in i9xx_update_cursor()
8748 POSTING_READ(CURBASE(pipe)); in i9xx_update_cursor()
8760 int pipe = intel_crtc->pipe; in intel_crtc_update_cursor() local
8795 I915_WRITE(CURPOS(pipe), pos); in intel_crtc_update_cursor()
9122 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_get_load_detect_pipe()
9225 int pipe = pipe_config->cpu_transcoder; in i9xx_crtc_clock_get() local
9274 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); in i9xx_crtc_clock_get()
9359 enum pipe pipe = intel_crtc->pipe; in intel_crtc_mode_get() local
9372 pipe_config.cpu_transcoder = (enum transcoder) pipe; in intel_crtc_mode_get()
9374 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
9375 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); in intel_crtc_mode_get()
9376 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); in intel_crtc_mode_get()
9411 int pipe = intel_crtc->pipe; in intel_decrease_pllclock() local
9412 int dpll_reg = DPLL(pipe); in intel_decrease_pllclock()
9417 assert_panel_unlocked(dev_priv, pipe); in intel_decrease_pllclock()
9422 intel_wait_for_vblank(dev, pipe); in intel_decrease_pllclock()
9502 enum pipe pipe = to_intel_crtc(work->crtc)->pipe; in intel_unpin_work_fn() local
9514 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); in intel_unpin_work_fn()
9554 void intel_finish_page_flip(struct drm_device *dev, int pipe) in intel_finish_page_flip() argument
9557 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_finish_page_flip()
9612 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), in page_flip_finished()
9745 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen4_queue_flip()
9781 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; in intel_gen6_queue_flip()
9918 const enum pipe pipe = intel_crtc->pipe; in skl_do_mmio_flip() local
9921 ctl = I915_READ(PLANE_CTL(pipe, 0)); in skl_do_mmio_flip()
9938 I915_WRITE(PLANE_CTL(pipe, 0), ctl); in skl_do_mmio_flip()
9939 I915_WRITE(PLANE_STRIDE(pipe, 0), stride); in skl_do_mmio_flip()
9941 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); in skl_do_mmio_flip()
9942 POSTING_READ(PLANE_SURF(pipe, 0)); in skl_do_mmio_flip()
10081 void intel_check_page_flip(struct drm_device *dev, int pipe) in intel_check_page_flip() argument
10084 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_check_page_flip()
10096 drm_vblank_count(dev, pipe)); in intel_check_page_flip()
10113 enum pipe pipe = intel_crtc->pipe; in intel_crtc_page_flip() local
10196 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; in intel_crtc_page_flip()
10243 INTEL_FRONTBUFFER_PRIMARY(pipe)); in intel_crtc_page_flip()
10246 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); in intel_crtc_page_flip()
10278 drm_send_vblank_event(dev, pipe, event); in intel_crtc_page_flip()
10489 context, pipe_name(crtc->pipe)); in intel_dump_pipe_config()
10667 (enum transcoder) to_intel_crtc(crtc)->pipe; in intel_modeset_pipe_config()
10791 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; in intel_modeset_affected_pipes()
10796 1 << connector->new_encoder->new_crtc->pipe; in intel_modeset_affected_pipes()
10806 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; in intel_modeset_affected_pipes()
10810 *prepare_pipes |= 1 << encoder->new_crtc->pipe; in intel_modeset_affected_pipes()
10819 *disable_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10821 *prepare_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10828 *prepare_pipes |= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10847 *modeset_pipes &= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10848 *prepare_pipes &= 1 << intel_crtc->pipe; in intel_modeset_affected_pipes()
10882 if (prepare_pipes & (1 << intel_crtc->pipe)) in intel_modeset_update_state()
10902 if (prepare_pipes & (1 << intel_crtc->pipe)) { in intel_modeset_update_state()
10940 if (mask & (1 <<(intel_crtc)->pipe))
11147 const enum pipe pipe = intel_crtc->pipe; in check_wm_state() local
11153 for_each_plane(dev_priv, pipe, plane) { in check_wm_state()
11154 hw_entry = &hw_ddb.plane[pipe][plane]; in check_wm_state()
11155 sw_entry = &sw_ddb->plane[pipe][plane]; in check_wm_state()
11162 pipe_name(pipe), plane + 1, in check_wm_state()
11168 hw_entry = &hw_ddb.cursor[pipe]; in check_wm_state()
11169 sw_entry = &sw_ddb->cursor[pipe]; in check_wm_state()
11176 pipe_name(pipe), in check_wm_state()
11206 enum pipe pipe, tracked_pipe; in check_encoder_state() local
11236 active = encoder->get_hw_state(encoder, &pipe); in check_encoder_state()
11245 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; in check_encoder_state()
11246 I915_STATE_WARN(active && pipe != tracked_pipe, in check_encoder_state()
11249 tracked_pipe, pipe); in check_encoder_state()
11294 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in check_crtc_state()
11295 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in check_crtc_state()
11299 enum pipe pipe; in check_crtc_state() local
11302 if (encoder->get_hw_state(encoder, &pipe)) in check_crtc_state()
11926 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); in intel_modeset_stage_output_state()
12060 pipe_name(crtc->pipe)); in disable_crtc_nofb()
12295 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); in ibx_pch_dpll_disable()
12381 enum pipe pipe = intel_plane->pipe; in intel_prepare_plane_fb() local
12392 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); in intel_prepare_plane_fb()
12395 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); in intel_prepare_plane_fb()
12398 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); in intel_prepare_plane_fb()
12514 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); in intel_check_primary_plane()
12582 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); in intel_begin_crtc_commit()
12585 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); in intel_begin_crtc_commit()
12588 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); in intel_begin_crtc_commit()
12636 intel_wait_for_vblank(dev, intel_crtc->pipe); in intel_finish_crtc_commit()
12684 int pipe) in intel_primary_plane_create() argument
12704 primary->pipe = pipe; in intel_primary_plane_create()
12705 primary->plane = pipe; in intel_primary_plane_create()
12709 primary->plane = !pipe; in intel_primary_plane_create()
12796 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); in intel_check_cursor_plane()
12838 int pipe) in intel_cursor_plane_create() argument
12856 cursor->pipe = pipe; in intel_cursor_plane_create()
12857 cursor->plane = pipe; in intel_cursor_plane_create()
12884 static void intel_crtc_init(struct drm_device *dev, int pipe) in intel_crtc_init() argument
12903 primary = intel_primary_plane_create(dev, pipe); in intel_crtc_init()
12907 cursor = intel_cursor_plane_create(dev, pipe); in intel_crtc_init()
12927 intel_crtc->pipe = pipe; in intel_crtc_init()
12928 intel_crtc->plane = pipe; in intel_crtc_init()
12931 intel_crtc->plane = !pipe; in intel_crtc_init()
12938 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || in intel_crtc_init()
12941 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
12947 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); in intel_crtc_init()
12959 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) in intel_get_pipe_from_connector()
12969 return to_intel_crtc(encoder->crtc)->pipe; in intel_get_pipe_from_connector()
12987 pipe_from_crtc_id->pipe = crtc->pipe; in intel_get_pipe_from_crtc_id()
13768 enum pipe pipe; in intel_modeset_init() local
13839 for_each_pipe(dev_priv, pipe) { in intel_modeset_init()
13840 intel_crtc_init(dev, pipe); in intel_modeset_init()
13841 for_each_sprite(dev_priv, pipe, sprite) { in intel_modeset_init()
13842 ret = intel_plane_init(dev, pipe, sprite); in intel_modeset_init()
13845 pipe_name(pipe), sprite_name(pipe, sprite), ret); in intel_modeset_init()
13925 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) in intel_check_plane_mapping()
13989 crtc->pipe == PIPE_A && !crtc->active) { in intel_sanitize_crtc()
14133 enum pipe pipe; in intel_modeset_readout_hw_state() local
14166 pll->config.crtc_mask |= 1 << crtc->pipe; in intel_modeset_readout_hw_state()
14178 pipe = 0; in intel_modeset_readout_hw_state()
14180 if (encoder->get_hw_state(encoder, &pipe)) { in intel_modeset_readout_hw_state()
14181 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_readout_hw_state()
14193 pipe_name(pipe)); in intel_modeset_readout_hw_state()
14218 enum pipe pipe; in intel_modeset_setup_hw_state() local
14245 for_each_pipe(dev_priv, pipe) { in intel_modeset_setup_hw_state()
14246 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
14278 for_each_pipe(dev_priv, pipe) { in intel_modeset_setup_hw_state()
14280 dev_priv->pipe_to_crtc_mapping[pipe]; in intel_modeset_setup_hw_state()
14323 to_intel_crtc(c)->pipe); in intel_modeset_gem_init()
14454 } pipe[I915_MAX_PIPES]; member
14505 error->pipe[i].power_domain_on = in intel_display_capture_error_state()
14508 if (!error->pipe[i].power_domain_on) in intel_display_capture_error_state()
14528 error->pipe[i].source = I915_READ(PIPESRC(i)); in intel_display_capture_error_state()
14531 error->pipe[i].stat = I915_READ(PIPESTAT(i)); in intel_display_capture_error_state()
14581 error->pipe[i].power_domain_on ? "on" : "off"); in intel_display_print_error_state()
14582 err_printf(m, " SRC: %08x\n", error->pipe[i].source); in intel_display_print_error_state()
14583 err_printf(m, " STAT: %08x\n", error->pipe[i].stat); in intel_display_print_error_state()