127 	intel_p2_t	    p2;  member
159 	.p2 = { .dot_limit = 165000,
172 	.p2 = { .dot_limit = 165000,
185 	.p2 = { .dot_limit = 165000,
198 	.p2 = { .dot_limit = 200000,
211 	.p2 = { .dot_limit = 112000,
225 	.p2 = { .dot_limit = 270000,
240 	.p2 = { .dot_limit = 165000,
253 	.p2 = { .dot_limit = 0,
267 	.p2 = { .dot_limit = 0,
283 	.p2 = { .dot_limit = 200000,
296 	.p2 = { .dot_limit = 112000,
314 	.p2 = { .dot_limit = 225000,
327 	.p2 = { .dot_limit = 225000,
340 	.p2 = { .dot_limit = 225000,
354 	.p2 = { .dot_limit = 225000,
367 	.p2 = { .dot_limit = 225000,
384 	.p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
400 	.p2 = {	.p2_slow = 1, .p2_fast = 14 },
406 	clock->p = clock->p1 * clock->p2;  in vlv_clock()
547 	clock->p = clock->p1 * clock->p2;  in pineview_clock()
562 	clock->p = clock->p1 * clock->p2;  in i9xx_clock()
572 	clock->p = clock->p1 * clock->p2;  in chv_clock()
639 			clock.p2 = limit->p2.p2_fast;  in i9xx_find_best_dpll()
641 			clock.p2 = limit->p2.p2_slow;  in i9xx_find_best_dpll()
643 		if (target < limit->p2.dot_limit)  in i9xx_find_best_dpll()
644 			clock.p2 = limit->p2.p2_slow;  in i9xx_find_best_dpll()
646 			clock.p2 = limit->p2.p2_fast;  in i9xx_find_best_dpll()
702 			clock.p2 = limit->p2.p2_fast;  in pnv_find_best_dpll()
704 			clock.p2 = limit->p2.p2_slow;  in pnv_find_best_dpll()
706 		if (target < limit->p2.dot_limit)  in pnv_find_best_dpll()
707 			clock.p2 = limit->p2.p2_slow;  in pnv_find_best_dpll()
709 			clock.p2 = limit->p2.p2_fast;  in pnv_find_best_dpll()
762 			clock.p2 = limit->p2.p2_fast;  in g4x_find_best_dpll()
764 			clock.p2 = limit->p2.p2_slow;  in g4x_find_best_dpll()
766 		if (target < limit->p2.dot_limit)  in g4x_find_best_dpll()
767 			clock.p2 = limit->p2.p2_slow;  in g4x_find_best_dpll()
769 			clock.p2 = limit->p2.p2_fast;  in g4x_find_best_dpll()
865 			for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;  in vlv_find_best_dpll()
866 			     clock.p2 -= clock.p2 > 10 ? 2 : 1) {  in vlv_find_best_dpll()
867 				clock.p = clock.p1 * clock.p2;  in vlv_find_best_dpll()
923 		for (clock.p2 = limit->p2.p2_fast;  in chv_find_best_dpll()
924 				clock.p2 >= limit->p2.p2_slow;  in chv_find_best_dpll()
925 				clock.p2 -= clock.p2 > 10 ? 2 : 1) {  in chv_find_best_dpll()
928 			clock.p = clock.p1 * clock.p2;  in chv_find_best_dpll()
6232 	bestp2 = pipe_config->dpll.p2;  in vlv_prepare_pll()
6338 	bestp2 = pipe_config->dpll.p2;  in chv_prepare_pll()
6515 	switch (clock->p2) {  in i9xx_update_pll()
6571 		if (clock->p2 == 4)  in i8xx_update_pll()
6859 		crtc_state->dpll.p2 = clock.p2;  in i9xx_crtc_compute_clock()
6931 	clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;  in vlv_crtc_clock_get()
7030 	clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;  in chv_crtc_clock_get()
7814 	switch (crtc_state->dpll.p2) {  in ironlake_compute_dpll()
7864 		crtc_state->dpll.p2 = clock.p2;  in ironlake_crtc_compute_clock()
9255 			clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?  in i9xx_crtc_clock_get()
9259 			clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?  in i9xx_crtc_clock_get()
9281 				clock.p2 = 7;  in i9xx_crtc_clock_get()
9283 				clock.p2 = 14;  in i9xx_crtc_clock_get()
9292 				clock.p2 = 4;  in i9xx_crtc_clock_get()
9294 				clock.p2 = 2;  in i9xx_crtc_clock_get()