126 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;  member
156 	.m2 = { .min = 6, .max = 16 },
169 	.m2 = { .min = 6, .max = 16 },
182 	.m2 = { .min = 6, .max = 16 },
195 	.m2 = { .min = 3, .max = 7 },
208 	.m2 = { .min = 3, .max = 7 },
222 	.m2 = { .min = 5, .max = 11 },
237 	.m2 = { .min = 5, .max = 11 },
250 	.m2 = { .min = 5, .max = 11 },
264 	.m2 = { .min = 5, .max = 11 },
280 	.m2 = { .min = 0, .max = 254 },
293 	.m2 = { .min = 0, .max = 254 },
311 	.m2 = { .min = 5, .max = 9 },
324 	.m2 = { .min = 5, .max = 9 },
337 	.m2 = { .min = 5, .max = 9 },
351 	.m2 = { .min = 5, .max = 9 },
364 	.m2 = { .min = 5, .max = 9 },
382 	.m2 = { .min = 11, .max = 156 },
398 	.m2 = { .min = 24 << 22, .max = 175 << 22 },
405 	clock->m = clock->m1 * clock->m2;  in vlv_clock()
546 	clock->m = clock->m2 + 2;  in pineview_clock()
556 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
571 	clock->m = clock->m1 * clock->m2;  in chv_clock()
594 	if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)  in intel_PLL_is_valid()
600 		if (clock->m1 <= clock->m2)  in intel_PLL_is_valid()
653 		for (clock.m2 = limit->m2.min;  in i9xx_find_best_dpll()
654 		     clock.m2 <= limit->m2.max; clock.m2++) {  in i9xx_find_best_dpll()
655 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
716 		for (clock.m2 = limit->m2.min;  in pnv_find_best_dpll()
717 		     clock.m2 <= limit->m2.max; clock.m2++) {  in pnv_find_best_dpll()
779 			for (clock.m2 = limit->m2.max;  in g4x_find_best_dpll()
780 			     clock.m2 >= limit->m2.min; clock.m2--) {  in g4x_find_best_dpll()
872 					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,  in vlv_find_best_dpll()
908 	uint64_t m2;  in chv_find_best_dpll()  local
930 			m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *  in chv_find_best_dpll()
933 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
936 			clock.m2 = m2;  in chv_find_best_dpll()
6055 	return (1 << dpll->n) << 16 | dpll->m2;  in pnv_dpll_compute_fp()
6060 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
6230 	bestm2 = pipe_config->dpll.m2;  in vlv_prepare_pll()
6334 	bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;  in chv_prepare_pll()
6336 	bestm2 = pipe_config->dpll.m2 >> 22;  in chv_prepare_pll()
6857 		crtc_state->dpll.m2 = clock.m2;  in i9xx_crtc_compute_clock()
6928 	clock.m2 = mdiv & DPIO_M2DIV_MASK;  in vlv_crtc_clock_get()
7027 	clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);  in chv_crtc_clock_get()
7862 		crtc_state->dpll.m2 = clock.m2;  in ironlake_crtc_compute_clock()
9239 		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;  in i9xx_crtc_clock_get()
9242 		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;  in i9xx_crtc_clock_get()