126 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;  member
155 	.m1 = { .min = 18, .max = 26 },
168 	.m1 = { .min = 18, .max = 26 },
181 	.m1 = { .min = 18, .max = 26 },
194 	.m1 = { .min = 8, .max = 18 },
207 	.m1 = { .min = 8, .max = 18 },
221 	.m1 = { .min = 17, .max = 23 },
236 	.m1 = { .min = 16, .max = 23 },
249 	.m1 = { .min = 17, .max = 23 },
263 	.m1 = { .min = 17, .max = 23 },
279 	.m1 = { .min = 0, .max = 0 },
292 	.m1 = { .min = 0, .max = 0 },
310 	.m1 = { .min = 12, .max = 22 },
323 	.m1 = { .min = 12, .max = 22 },
336 	.m1 = { .min = 12, .max = 22 },
350 	.m1 = { .min = 12, .max = 22 },
363 	.m1 = { .min = 12, .max = 22 },
381 	.m1 = { .min = 2, .max = 3 },
397 	.m1 = { .min = 2, .max = 2 },
405 	clock->m = clock->m1 * clock->m2;  in vlv_clock()
556 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
571 	clock->m = clock->m1 * clock->m2;  in chv_clock()
596 	if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)  in intel_PLL_is_valid()
600 		if (clock->m1 <= clock->m2)  in intel_PLL_is_valid()
651 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in i9xx_find_best_dpll()
652 	     clock.m1++) {  in i9xx_find_best_dpll()
655 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
714 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in pnv_find_best_dpll()
715 	     clock.m1++) {  in pnv_find_best_dpll()
777 		for (clock.m1 = limit->m1.max;  in g4x_find_best_dpll()
778 		     clock.m1 >= limit->m1.min; clock.m1--) {  in g4x_find_best_dpll()
869 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {  in vlv_find_best_dpll()
873 								     refclk * clock.m1);  in vlv_find_best_dpll()
919 	clock.n = 1, clock.m1 = 2;  in chv_find_best_dpll()
931 					clock.n) << 22, refclk * clock.m1);  in chv_find_best_dpll()
933 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
6060 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
6229 	bestm1 = pipe_config->dpll.m1;  in vlv_prepare_pll()
6335 	bestm1 = pipe_config->dpll.m1;  in chv_prepare_pll()
6856 		crtc_state->dpll.m1 = clock.m1;  in i9xx_crtc_compute_clock()
6927 	clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;  in vlv_crtc_clock_get()
7026 	clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;  in chv_crtc_clock_get()
7861 		crtc_state->dpll.m1 = clock.m1;  in ironlake_crtc_compute_clock()
9236 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;  in i9xx_crtc_clock_get()