Lines Matching refs:gen
1028 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
1205 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1347 if (INTEL_INFO(dev)->gen >= 4) { in assert_planes_disabled()
1375 if (INTEL_INFO(dev)->gen >= 9) { in assert_sprites_disabled()
1390 } else if (INTEL_INFO(dev)->gen >= 7) { in assert_sprites_disabled()
1396 } else if (INTEL_INFO(dev)->gen >= 5) { in assert_sprites_disabled()
1683 BUG_ON(INTEL_INFO(dev)->gen >= 5); in i9xx_enable_pll()
1708 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_enable_pll()
1915 BUG_ON(INTEL_INFO(dev)->gen < 5); in intel_disable_shared_dpll()
2192 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); in intel_flush_primary_plane()
2261 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) in need_vtd_wa()
2370 if (INTEL_INFO(dev)->gen >= 9) in intel_pin_and_fence_fb_obj()
2374 else if (INTEL_INFO(dev)->gen >= 4) in intel_pin_and_fence_fb_obj()
2380 if (INTEL_INFO(dev)->gen >= 9) in intel_pin_and_fence_fb_obj()
2389 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, in intel_pin_and_fence_fb_obj()
2681 if (INTEL_INFO(dev)->gen >= 4) in i9xx_update_primary_plane()
2699 if (INTEL_INFO(dev)->gen < 4) { in i9xx_update_primary_plane()
2749 if (INTEL_INFO(dev)->gen >= 4 && in i9xx_update_primary_plane()
2758 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2784 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_primary_plane()
2910 if (INTEL_INFO(dev)->gen == 2) in intel_fb_stride_alignment()
3094 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_prepare_reset()
3125 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { in intel_finish_reset()
5823 if (INTEL_INFO(dev)->gen < 4) { in intel_crtc_compute_config()
5857 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && in intel_crtc_compute_config()
5863 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { in intel_crtc_compute_config()
6143 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_set_m_n()
6152 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && in intel_cpu_transcoder_set_m_n()
6529 if (INTEL_INFO(dev)->gen >= 4) in i9xx_update_pll()
6543 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_pll()
6618 if (INTEL_INFO(dev)->gen > 3) in intel_set_pipe_timings()
6766 if (INTEL_INFO(dev)->gen < 4 || in i9xx_set_pipeconf()
6886 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) in i9xx_get_pfit_config()
6894 if (INTEL_INFO(dev)->gen < 4) { in i9xx_get_pfit_config()
6904 if (INTEL_INFO(dev)->gen < 5) in i9xx_get_pfit_config()
6964 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_initial_plane_config()
6976 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_initial_plane_config()
7075 if (INTEL_INFO(dev)->gen < 4) in i9xx_get_pipe_config()
7082 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_get_pipe_config()
7603 if (INTEL_INFO(dev)->gen > 6) { in intel_set_pipe_csc()
7649 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { in haswell_set_pipeconf()
7925 if (INTEL_INFO(dev)->gen >= 5) { in intel_cpu_transcoder_get_m_n()
7937 if (m2_n2 && INTEL_INFO(dev)->gen < 8 && in intel_cpu_transcoder_get_m_n()
8125 if (INTEL_INFO(dev)->gen >= 4) { in ironlake_get_initial_plane_config()
8561 if (INTEL_INFO(dev)->gen < 9 && in haswell_get_ddi_port_state()
9439 if (INTEL_INFO(dev)->gen >= 6) in intel_mark_busy()
9461 if (INTEL_INFO(dev)->gen >= 6) in intel_mark_idle()
9592 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) in page_flip_finished()
9898 if (INTEL_INFO(ring->dev)->gen < 5) in use_mmio_flip()
9985 if (INTEL_INFO(dev)->gen >= 9) in intel_do_mmio_flip()
10069 if (INTEL_INFO(dev)->gen >= 4) in __intel_pageflip_stall_check()
10134 if (INTEL_INFO(dev)->gen > 3 && in intel_crtc_page_flip()
10195 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) in intel_crtc_page_flip()
10205 } else if (INTEL_INFO(dev)->gen >= 7) { in intel_crtc_page_flip()
10425 if (WARN_ON(INTEL_INFO(dev)->gen > 3)) in compute_baseline_pipe_bpp()
10433 if (WARN_ON(INTEL_INFO(dev)->gen < 4)) in compute_baseline_pipe_bpp()
10444 if (WARN_ON(INTEL_INFO(dev)->gen < 4)) in compute_baseline_pipe_bpp()
11014 if (INTEL_INFO(dev)->gen < 8) { in intel_pipe_config_compare()
11052 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || in intel_pipe_config_compare()
11087 if (INTEL_INFO(dev)->gen < 4) in intel_pipe_config_compare()
11116 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) in intel_pipe_config_compare()
11139 if (INTEL_INFO(dev)->gen < 9) in check_wm_state()
12487 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && in intel_check_primary_plane()
12708 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) in intel_primary_plane_create()
12711 if (INTEL_INFO(dev)->gen <= 3) { in intel_primary_plane_create()
12724 if (INTEL_INFO(dev)->gen >= 4) { in intel_primary_plane_create()
12867 if (INTEL_INFO(dev)->gen >= 4) { in intel_cursor_plane_create()
12929 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { in intel_crtc_init()
13029 if (INTEL_INFO(dev)->gen >= 9) in intel_crt_present()
13233 u32 gen = INTEL_INFO(dev)->gen; in intel_fb_pitch_limit() local
13235 if (gen >= 9) { in intel_fb_pitch_limit()
13240 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { in intel_fb_pitch_limit()
13242 } else if (gen >= 4) { in intel_fb_pitch_limit()
13247 } else if (gen >= 3) { in intel_fb_pitch_limit()
13290 if (INTEL_INFO(dev)->gen < 9) { in intel_framebuffer_init()
13338 if (INTEL_INFO(dev)->gen > 3) { in intel_framebuffer_init()
13350 if (INTEL_INFO(dev)->gen < 4) { in intel_framebuffer_init()
13360 if (INTEL_INFO(dev)->gen < 5) { in intel_framebuffer_init()
13440 if (INTEL_INFO(dev)->gen >= 9) { in intel_init_display()
13538 switch (INTEL_INFO(dev)->gen) { in intel_init_display()
13951 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { in intel_sanitize_crtc()
14413 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; in intel_modeset_vga_set_state()
14517 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_capture_error_state()
14521 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_capture_error_state()
14523 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_capture_error_state()
14588 if (INTEL_INFO(dev)->gen <= 3) { in intel_display_print_error_state()
14592 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) in intel_display_print_error_state()
14594 if (INTEL_INFO(dev)->gen >= 4) { in intel_display_print_error_state()