Lines Matching refs:dpio_val
6330 u32 dpio_val; in chv_prepare_pll() local
6340 dpio_val = 0; in chv_prepare_pll()
6371 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll()
6372 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); in chv_prepare_pll()
6373 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); in chv_prepare_pll()
6375 dpio_val |= DPIO_CHV_FRAC_DIV_EN; in chv_prepare_pll()
6376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); in chv_prepare_pll()
6379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll()
6380 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | in chv_prepare_pll()
6382 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); in chv_prepare_pll()
6384 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; in chv_prepare_pll()
6385 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); in chv_prepare_pll()
6412 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); in chv_prepare_pll()
6413 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; in chv_prepare_pll()
6414 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); in chv_prepare_pll()
6415 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); in chv_prepare_pll()