126 	intel_range_t   dot, vco, n, m, m1, m2, p, p1;  member
151 	.dot = { .min = 25000, .max = 350000 },
164 	.dot = { .min = 25000, .max = 350000 },
177 	.dot = { .min = 25000, .max = 350000 },
190 	.dot = { .min = 20000, .max = 400000 },
203 	.dot = { .min = 20000, .max = 400000 },
217 	.dot = { .min = 25000, .max = 270000 },
232 	.dot = { .min = 22000, .max = 400000 },
245 	.dot = { .min = 20000, .max = 115000 },
259 	.dot = { .min = 80000, .max = 224000 },
273 	.dot = { .min = 20000, .max = 400000},
288 	.dot = { .min = 20000, .max = 400000 },
306 	.dot = { .min = 25000, .max = 350000 },
319 	.dot = { .min = 25000, .max = 350000 },
332 	.dot = { .min = 25000, .max = 350000 },
346 	.dot = { .min = 25000, .max = 350000 },
359 	.dot = { .min = 25000, .max = 350000 },
378 	.dot = { .min = 25000 * 5, .max = 270000 * 5 },
394 	.dot = { .min = 25000 * 5, .max = 540000 * 5},
410 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in vlv_clock()
551 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in pineview_clock()
566 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in i9xx_clock()
577 	clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);  in chv_clock()
615 	if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)  in intel_PLL_is_valid()
671 					this_err = abs(clock.dot - target);  in i9xx_find_best_dpll()
732 					this_err = abs(clock.dot - target);  in pnv_find_best_dpll()
790 					this_err = abs(clock.dot - target);  in g4x_find_best_dpll()
828 				abs(target_freq - calculated_clock->dot),  in vlv_PLL_is_optimal()
6936 	pipe_config->port_clock = clock.dot / 5;  in vlv_crtc_clock_get()
7035 	pipe_config->port_clock = clock.dot / 5;  in chv_crtc_clock_get()
9305 	pipe_config->port_clock = clock.dot;  in i9xx_crtc_clock_get()