2220 	dev_priv->display.update_primary_plane(crtc, plane->fb,  in intel_enable_primary_hw_plane()
2254 	dev_priv->display.update_primary_plane(crtc, plane->fb,  in intel_disable_primary_hw_plane()
3040 	if (dev_priv->display.disable_fbc)  in intel_pipe_set_base_atomic()
3041 		dev_priv->display.disable_fbc(dev);  in intel_pipe_set_base_atomic()
3043 	dev_priv->display.update_primary_plane(crtc, fb, x, y);  in intel_pipe_set_base_atomic()
3076 			dev_priv->display.update_primary_plane(crtc,  in intel_update_primary_planes()
3105 			dev_priv->display.crtc_disable(&crtc->base);  in intel_prepare_reset()
3146 	if (dev_priv->display.hpd_irq_setup)  in intel_finish_reset()
3147 		dev_priv->display.hpd_irq_setup(dev);  in intel_finish_reset()
4004 	dev_priv->display.fdi_link_train(crtc);  in ironlake_pch_enable()
4664 		dev_priv->display.fdi_link_train(crtc);  in haswell_crtc_enable()
4984 	if (dev_priv->display.modeset_global_resources)  in modeset_update_crtc_power_domains()
4985 		dev_priv->display.modeset_global_resources(state);  in modeset_update_crtc_power_domains()
5017 	dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);  in vlv_update_cdclk()
5035 	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);  in valleyview_set_cdclk()
5099 	WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);  in cherryview_set_cdclk()
5518 			dev_priv->display.crtc_enable(crtc);  in intel_crtc_control()
5522 			dev_priv->display.crtc_disable(crtc);  in intel_crtc_control()
5556 	dev_priv->display.crtc_disable(crtc);  in intel_crtc_disable()
5557 	dev_priv->display.off(crtc);  in intel_crtc_disable()
5825 			dev_priv->display.get_display_clock_speed(dev);  in intel_crtc_compute_config()
6833 		ok = dev_priv->display.find_dpll(limit, crtc_state,  in i9xx_crtc_compute_clock()
6849 				dev_priv->display.find_dpll(limit, crtc_state,  in i9xx_crtc_compute_clock()
7699 	ret = dev_priv->display.find_dpll(limit, crtc_state,  in ironlake_compute_clocks()
7713 			dev_priv->display.find_dpll(limit, crtc_state,  in ironlake_compute_clocks()
10230 		ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,  in intel_crtc_page_flip()
11290 		active = dev_priv->display.get_pipe_config(crtc,  in check_crtc_state()
11491 	if (!dev_priv->display.crtc_compute_clock)  in __intel_set_mode_setup_plls()
11500 		ret = dev_priv->display.crtc_compute_clock(intel_crtc,  in __intel_set_mode_setup_plls()
11565 			dev_priv->display.crtc_disable(&intel_crtc->base);  in __intel_set_mode()
11615 		dev_priv->display.crtc_enable(&intel_crtc->base);  in __intel_set_mode()
12550 			dev_priv->display.update_primary_plane(crtc, plane->fb,  in intel_commit_primary_plane()
13430 		dev_priv->display.find_dpll = g4x_find_best_dpll;  in intel_init_display()
13432 		dev_priv->display.find_dpll = chv_find_best_dpll;  in intel_init_display()
13434 		dev_priv->display.find_dpll = vlv_find_best_dpll;  in intel_init_display()
13436 		dev_priv->display.find_dpll = pnv_find_best_dpll;  in intel_init_display()
13438 		dev_priv->display.find_dpll = i9xx_find_best_dpll;  in intel_init_display()
13441 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;  in intel_init_display()
13442 		dev_priv->display.get_initial_plane_config =  in intel_init_display()
13444 		dev_priv->display.crtc_compute_clock =  in intel_init_display()
13446 		dev_priv->display.crtc_enable = haswell_crtc_enable;  in intel_init_display()
13447 		dev_priv->display.crtc_disable = haswell_crtc_disable;  in intel_init_display()
13448 		dev_priv->display.off = ironlake_crtc_off;  in intel_init_display()
13449 		dev_priv->display.update_primary_plane =  in intel_init_display()
13452 		dev_priv->display.get_pipe_config = haswell_get_pipe_config;  in intel_init_display()
13453 		dev_priv->display.get_initial_plane_config =  in intel_init_display()
13455 		dev_priv->display.crtc_compute_clock =  in intel_init_display()
13457 		dev_priv->display.crtc_enable = haswell_crtc_enable;  in intel_init_display()
13458 		dev_priv->display.crtc_disable = haswell_crtc_disable;  in intel_init_display()
13459 		dev_priv->display.off = ironlake_crtc_off;  in intel_init_display()
13460 		dev_priv->display.update_primary_plane =  in intel_init_display()
13463 		dev_priv->display.get_pipe_config = ironlake_get_pipe_config;  in intel_init_display()
13464 		dev_priv->display.get_initial_plane_config =  in intel_init_display()
13466 		dev_priv->display.crtc_compute_clock =  in intel_init_display()
13468 		dev_priv->display.crtc_enable = ironlake_crtc_enable;  in intel_init_display()
13469 		dev_priv->display.crtc_disable = ironlake_crtc_disable;  in intel_init_display()
13470 		dev_priv->display.off = ironlake_crtc_off;  in intel_init_display()
13471 		dev_priv->display.update_primary_plane =  in intel_init_display()
13474 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;  in intel_init_display()
13475 		dev_priv->display.get_initial_plane_config =  in intel_init_display()
13477 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;  in intel_init_display()
13478 		dev_priv->display.crtc_enable = valleyview_crtc_enable;  in intel_init_display()
13479 		dev_priv->display.crtc_disable = i9xx_crtc_disable;  in intel_init_display()
13480 		dev_priv->display.off = i9xx_crtc_off;  in intel_init_display()
13481 		dev_priv->display.update_primary_plane =  in intel_init_display()
13484 		dev_priv->display.get_pipe_config = i9xx_get_pipe_config;  in intel_init_display()
13485 		dev_priv->display.get_initial_plane_config =  in intel_init_display()
13487 		dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;  in intel_init_display()
13488 		dev_priv->display.crtc_enable = i9xx_crtc_enable;  in intel_init_display()
13489 		dev_priv->display.crtc_disable = i9xx_crtc_disable;  in intel_init_display()
13490 		dev_priv->display.off = i9xx_crtc_off;  in intel_init_display()
13491 		dev_priv->display.update_primary_plane =  in intel_init_display()
13497 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13500 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13503 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13506 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13509 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13512 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13515 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13518 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13521 		dev_priv->display.get_display_clock_speed =  in intel_init_display()
13525 		dev_priv->display.fdi_link_train = ironlake_fdi_link_train;  in intel_init_display()
13527 		dev_priv->display.fdi_link_train = gen6_fdi_link_train;  in intel_init_display()
13530 		dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;  in intel_init_display()
13532 		dev_priv->display.fdi_link_train = hsw_fdi_link_train;  in intel_init_display()
13534 		dev_priv->display.modeset_global_resources =  in intel_init_display()
13540 		dev_priv->display.queue_flip = intel_gen2_queue_flip;  in intel_init_display()
13544 		dev_priv->display.queue_flip = intel_gen3_queue_flip;  in intel_init_display()
13549 		dev_priv->display.queue_flip = intel_gen4_queue_flip;  in intel_init_display()
13553 		dev_priv->display.queue_flip = intel_gen6_queue_flip;  in intel_init_display()
13557 		dev_priv->display.queue_flip = intel_gen7_queue_flip;  in intel_init_display()
13563 		dev_priv->display.queue_flip = intel_default_queue_flip;  in intel_init_display()
13875 		if (dev_priv->display.get_initial_plane_config) {  in intel_modeset_init()
13876 			dev_priv->display.get_initial_plane_config(crtc,  in intel_modeset_init()
13964 		dev_priv->display.crtc_disable(&crtc->base);  in intel_sanitize_crtc()
14144 		crtc->active = dev_priv->display.get_pipe_config(crtc,  in intel_modeset_readout_hw_state()