Lines Matching refs:dev_priv
133 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pch_rawclk() local
144 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fdi_link_freq() local
977 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, in intel_pipe_to_cpu_transcoder() argument
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_pipe_to_cpu_transcoder()
988 struct drm_i915_private *dev_priv = dev->dev_private; in pipe_dsl_stopped() local
1024 struct drm_i915_private *dev_priv = dev->dev_private; in intel_wait_for_pipe_off() local
1049 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, in ibx_digital_port_connected() argument
1054 if (HAS_PCH_IBX(dev_priv->dev)) { in ibx_digital_port_connected()
1093 void assert_pll(struct drm_i915_private *dev_priv, in assert_pll() argument
1109 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) in assert_dsi_pll() argument
1114 mutex_lock(&dev_priv->dpio_lock); in assert_dsi_pll()
1115 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); in assert_dsi_pll()
1116 mutex_unlock(&dev_priv->dpio_lock); in assert_dsi_pll()
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_crtc_to_shared_dpll() local
1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll]; in intel_crtc_to_shared_dpll()
1138 void assert_shared_dpll(struct drm_i915_private *dev_priv, in assert_shared_dpll() argument
1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); in assert_shared_dpll()
1155 static void assert_fdi_tx(struct drm_i915_private *dev_priv, in assert_fdi_tx() argument
1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in assert_fdi_tx()
1164 if (HAS_DDI(dev_priv->dev)) { in assert_fdi_tx()
1181 static void assert_fdi_rx(struct drm_i915_private *dev_priv, in assert_fdi_rx() argument
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, in assert_fdi_tx_pll_enabled() argument
1205 if (INTEL_INFO(dev_priv->dev)->gen == 5) in assert_fdi_tx_pll_enabled()
1209 if (HAS_DDI(dev_priv->dev)) in assert_fdi_tx_pll_enabled()
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, in assert_fdi_rx_pll() argument
1232 void assert_panel_unlocked(struct drm_i915_private *dev_priv, in assert_panel_unlocked() argument
1235 struct drm_device *dev = dev_priv->dev; in assert_panel_unlocked()
1274 static void assert_cursor(struct drm_i915_private *dev_priv, in assert_cursor() argument
1277 struct drm_device *dev = dev_priv->dev; in assert_cursor()
1292 void assert_pipe(struct drm_i915_private *dev_priv, in assert_pipe() argument
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in assert_pipe()
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in assert_pipe()
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in assert_pipe()
1306 if (!intel_display_power_is_enabled(dev_priv, in assert_pipe()
1320 static void assert_plane(struct drm_i915_private *dev_priv, in assert_plane() argument
1338 static void assert_planes_disabled(struct drm_i915_private *dev_priv, in assert_planes_disabled() argument
1341 struct drm_device *dev = dev_priv->dev; in assert_planes_disabled()
1357 for_each_pipe(dev_priv, i) { in assert_planes_disabled()
1368 static void assert_sprites_disabled(struct drm_i915_private *dev_priv, in assert_sprites_disabled() argument
1371 struct drm_device *dev = dev_priv->dev; in assert_sprites_disabled()
1376 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1383 for_each_sprite(dev_priv, pipe, sprite) { in assert_sprites_disabled()
1411 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) in ibx_assert_pch_refclk_enabled() argument
1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); in ibx_assert_pch_refclk_enabled()
1424 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, in assert_pch_transcoder_disabled() argument
1439 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, in dp_pipe_enabled() argument
1445 if (HAS_PCH_CPT(dev_priv->dev)) { in dp_pipe_enabled()
1450 } else if (IS_CHERRYVIEW(dev_priv->dev)) { in dp_pipe_enabled()
1460 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, in hdmi_pipe_enabled() argument
1466 if (HAS_PCH_CPT(dev_priv->dev)) { in hdmi_pipe_enabled()
1469 } else if (IS_CHERRYVIEW(dev_priv->dev)) { in hdmi_pipe_enabled()
1479 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, in lvds_pipe_enabled() argument
1485 if (HAS_PCH_CPT(dev_priv->dev)) { in lvds_pipe_enabled()
1495 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, in adpa_pipe_enabled() argument
1500 if (HAS_PCH_CPT(dev_priv->dev)) { in adpa_pipe_enabled()
1510 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, in assert_pch_dp_disabled() argument
1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), in assert_pch_dp_disabled()
1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 in assert_pch_dp_disabled()
1523 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, in assert_pch_hdmi_disabled() argument
1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), in assert_pch_hdmi_disabled()
1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 in assert_pch_hdmi_disabled()
1536 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, in assert_pch_ports_disabled() argument
1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); in assert_pch_ports_disabled()
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); in assert_pch_ports_disabled()
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); in assert_pch_ports_disabled()
1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), in assert_pch_ports_disabled()
1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); in assert_pch_ports_disabled()
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); in assert_pch_ports_disabled()
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); in assert_pch_ports_disabled()
1565 struct drm_i915_private *dev_priv = dev->dev_private; in intel_init_dpio() local
1587 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_enable_pll() local
1591 assert_pipe_disabled(dev_priv, crtc->pipe); in vlv_enable_pll()
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); in vlv_enable_pll()
1597 if (IS_MOBILE(dev_priv->dev)) in vlv_enable_pll()
1598 assert_panel_unlocked(dev_priv, crtc->pipe); in vlv_enable_pll()
1626 struct drm_i915_private *dev_priv = dev->dev_private; in chv_enable_pll() local
1631 assert_pipe_disabled(dev_priv, crtc->pipe); in chv_enable_pll()
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); in chv_enable_pll()
1635 mutex_lock(&dev_priv->dpio_lock); in chv_enable_pll()
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_enable_pll()
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); in chv_enable_pll()
1658 mutex_unlock(&dev_priv->dpio_lock); in chv_enable_pll()
1676 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_enable_pll() local
1680 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_enable_pll()
1687 assert_panel_unlocked(dev_priv, crtc->pipe); in i9xx_enable_pll()
1744 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_disable_pll() local
1758 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_disable_pll()
1759 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_disable_pll()
1763 assert_pipe_disabled(dev_priv, pipe); in i9xx_disable_pll()
1769 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in vlv_disable_pll() argument
1774 assert_pipe_disabled(dev_priv, pipe); in vlv_disable_pll()
1787 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) in chv_disable_pll() argument
1793 assert_pipe_disabled(dev_priv, pipe); in chv_disable_pll()
1802 mutex_lock(&dev_priv->dpio_lock); in chv_disable_pll()
1805 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll()
1807 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); in chv_disable_pll()
1811 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_disable_pll()
1813 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_disable_pll()
1815 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_disable_pll()
1817 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_disable_pll()
1820 mutex_unlock(&dev_priv->dpio_lock); in chv_disable_pll()
1823 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, in vlv_wait_port_ready() argument
1854 struct drm_i915_private *dev_priv = dev->dev_private; in intel_prepare_shared_dpll() local
1864 assert_shared_dpll_disabled(dev_priv, pll); in intel_prepare_shared_dpll()
1866 pll->mode_set(dev_priv, pll); in intel_prepare_shared_dpll()
1881 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_shared_dpll() local
1896 assert_shared_dpll_enabled(dev_priv, pll); in intel_enable_shared_dpll()
1901 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); in intel_enable_shared_dpll()
1904 pll->enable(dev_priv, pll); in intel_enable_shared_dpll()
1911 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_shared_dpll() local
1927 assert_shared_dpll_disabled(dev_priv, pll); in intel_disable_shared_dpll()
1931 assert_shared_dpll_enabled(dev_priv, pll); in intel_disable_shared_dpll()
1937 pll->disable(dev_priv, pll); in intel_disable_shared_dpll()
1940 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); in intel_disable_shared_dpll()
1943 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, in ironlake_enable_pch_transcoder() argument
1946 struct drm_device *dev = dev_priv->dev; in ironlake_enable_pch_transcoder()
1947 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in ironlake_enable_pch_transcoder()
1955 assert_shared_dpll_enabled(dev_priv, in ironlake_enable_pch_transcoder()
1959 assert_fdi_tx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1960 assert_fdi_rx_enabled(dev_priv, pipe); in ironlake_enable_pch_transcoder()
1975 if (HAS_PCH_IBX(dev_priv->dev)) { in ironlake_enable_pch_transcoder()
1986 if (HAS_PCH_IBX(dev_priv->dev) && in ironlake_enable_pch_transcoder()
1999 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, in lpt_enable_pch_transcoder() argument
2005 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); in lpt_enable_pch_transcoder()
2008 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); in lpt_enable_pch_transcoder()
2009 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); in lpt_enable_pch_transcoder()
2030 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, in ironlake_disable_pch_transcoder() argument
2033 struct drm_device *dev = dev_priv->dev; in ironlake_disable_pch_transcoder()
2037 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2038 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2041 assert_pch_ports_disabled(dev_priv, pipe); in ironlake_disable_pch_transcoder()
2060 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) in lpt_disable_pch_transcoder() argument
2087 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_pipe() local
2089 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, in intel_enable_pipe()
2095 assert_planes_disabled(dev_priv, pipe); in intel_enable_pipe()
2096 assert_cursor_disabled(dev_priv, pipe); in intel_enable_pipe()
2097 assert_sprites_disabled(dev_priv, pipe); in intel_enable_pipe()
2099 if (HAS_PCH_LPT(dev_priv->dev)) in intel_enable_pipe()
2109 if (!HAS_PCH_SPLIT(dev_priv->dev)) in intel_enable_pipe()
2111 assert_dsi_pll_enabled(dev_priv); in intel_enable_pipe()
2113 assert_pll_enabled(dev_priv, pipe); in intel_enable_pipe()
2117 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); in intel_enable_pipe()
2118 assert_fdi_tx_pll_enabled(dev_priv, in intel_enable_pipe()
2127 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in intel_enable_pipe()
2128 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); in intel_enable_pipe()
2148 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_disable_pipe() local
2158 assert_planes_disabled(dev_priv, pipe); in intel_disable_pipe()
2159 assert_cursor_disabled(dev_priv, pipe); in intel_disable_pipe()
2160 assert_sprites_disabled(dev_priv, pipe); in intel_disable_pipe()
2175 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && in intel_disable_pipe()
2176 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in intel_disable_pipe()
2188 void intel_flush_primary_plane(struct drm_i915_private *dev_priv, in intel_flush_primary_plane() argument
2191 struct drm_device *dev = dev_priv->dev; in intel_flush_primary_plane()
2209 struct drm_i915_private *dev_priv = dev->dev_private; in intel_enable_primary_hw_plane() local
2213 assert_pipe_enabled(dev_priv, intel_crtc->pipe); in intel_enable_primary_hw_plane()
2220 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_enable_primary_hw_plane()
2243 struct drm_i915_private *dev_priv = dev->dev_private; in intel_disable_primary_hw_plane() local
2254 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_disable_primary_hw_plane()
2360 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pin_and_fence_fb_obj() local
2418 intel_runtime_pm_get(dev_priv); in intel_pin_and_fence_fb_obj()
2420 dev_priv->mm.interruptible = false; in intel_pin_and_fence_fb_obj()
2437 dev_priv->mm.interruptible = true; in intel_pin_and_fence_fb_obj()
2438 intel_runtime_pm_put(dev_priv); in intel_pin_and_fence_fb_obj()
2444 dev_priv->mm.interruptible = true; in intel_pin_and_fence_fb_obj()
2445 intel_runtime_pm_put(dev_priv); in intel_pin_and_fence_fb_obj()
2610 struct drm_i915_private *dev_priv = dev->dev_private; in intel_find_initial_plane_obj() local
2656 dev_priv->preserve_bios_swizzle = true; in intel_find_initial_plane_obj()
2670 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_update_primary_plane() local
2799 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_update_primary_plane() local
2946 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_update_primary_plane() local
3038 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pipe_set_base_atomic() local
3040 if (dev_priv->display.disable_fbc) in intel_pipe_set_base_atomic()
3041 dev_priv->display.disable_fbc(dev); in intel_pipe_set_base_atomic()
3043 dev_priv->display.update_primary_plane(crtc, fb, x, y); in intel_pipe_set_base_atomic()
3063 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_primary_planes() local
3076 dev_priv->display.update_primary_plane(crtc, in intel_update_primary_planes()
3086 struct drm_i915_private *dev_priv = to_i915(dev); in intel_prepare_reset() local
3105 dev_priv->display.crtc_disable(&crtc->base); in intel_prepare_reset()
3111 struct drm_i915_private *dev_priv = to_i915(dev); in intel_finish_reset() local
3140 intel_runtime_pm_disable_interrupts(dev_priv); in intel_finish_reset()
3141 intel_runtime_pm_enable_interrupts(dev_priv); in intel_finish_reset()
3145 spin_lock_irq(&dev_priv->irq_lock); in intel_finish_reset()
3146 if (dev_priv->display.hpd_irq_setup) in intel_finish_reset()
3147 dev_priv->display.hpd_irq_setup(dev); in intel_finish_reset()
3148 spin_unlock_irq(&dev_priv->irq_lock); in intel_finish_reset()
3152 intel_hpd_init(dev_priv); in intel_finish_reset()
3161 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; in intel_finish_fb() local
3162 bool was_interruptible = dev_priv->mm.interruptible; in intel_finish_fb()
3173 dev_priv->mm.interruptible = false; in intel_finish_fb()
3175 dev_priv->mm.interruptible = was_interruptible; in intel_finish_fb()
3183 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_has_pending_flip() local
3187 if (i915_reset_in_progress(&dev_priv->gpu_error) || in intel_crtc_has_pending_flip()
3188 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in intel_crtc_has_pending_flip()
3201 struct drm_i915_private *dev_priv = dev->dev_private; in intel_update_pipe_size() local
3240 struct drm_i915_private *dev_priv = dev->dev_private; in intel_fdi_normal_train() local
3282 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_link_train() local
3288 assert_pipe_enabled(dev_priv, pipe); in ironlake_fdi_link_train()
3382 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_fdi_link_train() local
3514 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_manual_fdi_link_train() local
3632 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_pll_enable() local
3669 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_pll_disable() local
3698 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_fdi_disable() local
3773 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); in page_flip_completed() local
3787 wake_up_all(&dev_priv->pending_flip_queue); in page_flip_completed()
3788 queue_work(dev_priv->wq, &work->work); in page_flip_completed()
3797 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_wait_for_pending_flips() local
3799 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); in intel_crtc_wait_for_pending_flips()
3800 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, in intel_crtc_wait_for_pending_flips()
3824 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_program_iclkip() local
3829 mutex_lock(&dev_priv->dpio_lock); in lpt_program_iclkip()
3837 intel_sbi_write(dev_priv, SBI_SSCCTL6, in lpt_program_iclkip()
3838 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | in lpt_program_iclkip()
3881 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); in lpt_program_iclkip()
3888 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); in lpt_program_iclkip()
3891 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); in lpt_program_iclkip()
3894 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); in lpt_program_iclkip()
3897 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); in lpt_program_iclkip()
3899 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); in lpt_program_iclkip()
3906 mutex_unlock(&dev_priv->dpio_lock); in lpt_program_iclkip()
3913 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pch_transcoder_set_timings() local
3935 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_set_fdi_bc_bifurcation() local
3988 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pch_enable() local
3993 assert_pch_transcoder_disabled(dev_priv, pipe); in ironlake_pch_enable()
4004 dev_priv->display.fdi_link_train(crtc); in ironlake_pch_enable()
4031 assert_panel_unlocked(dev_priv, pipe); in ironlake_pch_enable()
4070 ironlake_enable_pch_transcoder(dev_priv, pipe); in ironlake_pch_enable()
4076 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_pch_enable() local
4080 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); in lpt_pch_enable()
4087 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); in lpt_pch_enable()
4114 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_get_shared_dpll() local
4118 if (HAS_PCH_IBX(dev_priv->dev)) { in intel_get_shared_dpll()
4121 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4131 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_get_shared_dpll()
4132 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4150 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_get_shared_dpll()
4151 pll = &dev_priv->shared_dplls[i]; in intel_get_shared_dpll()
4182 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, in intel_shared_dpll_start_config() argument
4188 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_shared_dpll_start_config()
4189 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_start_config()
4203 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_start_config()
4211 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) in intel_shared_dpll_commit() argument
4216 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_shared_dpll_commit()
4217 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_commit()
4227 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) in intel_shared_dpll_abort_config() argument
4232 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_shared_dpll_abort_config()
4233 pll = &dev_priv->shared_dplls[i]; in intel_shared_dpll_abort_config()
4244 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_verify_modeset() local
4259 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_pfit_enable() local
4272 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pfit_enable() local
4339 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_enable_ips() local
4347 assert_plane_enabled(dev_priv, crtc->plane); in hsw_enable_ips()
4349 mutex_lock(&dev_priv->rps.hw_lock); in hsw_enable_ips()
4350 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); in hsw_enable_ips()
4351 mutex_unlock(&dev_priv->rps.hw_lock); in hsw_enable_ips()
4372 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_disable_ips() local
4377 assert_plane_enabled(dev_priv, crtc->plane); in hsw_disable_ips()
4379 mutex_lock(&dev_priv->rps.hw_lock); in hsw_disable_ips()
4380 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); in hsw_disable_ips()
4381 mutex_unlock(&dev_priv->rps.hw_lock); in hsw_disable_ips()
4398 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_load_lut() local
4409 if (!HAS_PCH_SPLIT(dev_priv->dev)) { in intel_crtc_load_lut()
4411 assert_dsi_pll_enabled(dev_priv); in intel_crtc_load_lut()
4413 assert_pll_enabled(dev_priv, pipe); in intel_crtc_load_lut()
4445 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_dpms_overlay() local
4448 dev_priv->mm.interruptible = false; in intel_crtc_dpms_overlay()
4450 dev_priv->mm.interruptible = true; in intel_crtc_dpms_overlay()
4487 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_disable_planes() local
4493 if (dev_priv->fbc.crtc == intel_crtc) in intel_crtc_disable_planes()
4514 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_crtc_enable() local
4541 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4542 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); in ironlake_crtc_enable()
4554 assert_fdi_tx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4555 assert_fdi_rx_disabled(dev_priv, pipe); in ironlake_crtc_enable()
4622 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_crtc_enable() local
4656 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in haswell_crtc_enable()
4662 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, in haswell_crtc_enable()
4664 dev_priv->display.fdi_link_train(crtc); in haswell_crtc_enable()
4709 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_pfit_disable() local
4724 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_pfit_disable() local
4739 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_crtc_disable() local
4757 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); in ironlake_crtc_disable()
4770 ironlake_disable_pch_transcoder(dev_priv, pipe); in ironlake_crtc_disable()
4804 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_crtc_disable() local
4823 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, in haswell_crtc_disable()
4830 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); in haswell_crtc_disable()
4840 lpt_disable_pch_transcoder(dev_priv); in haswell_crtc_disable()
4869 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pfit_enable() local
4880 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_enable()
4964 struct drm_i915_private *dev_priv = dev->dev_private; in modeset_update_crtc_power_domains() local
4981 intel_display_power_get(dev_priv, domain); in modeset_update_crtc_power_domains()
4984 if (dev_priv->display.modeset_global_resources) in modeset_update_crtc_power_domains()
4985 dev_priv->display.modeset_global_resources(state); in modeset_update_crtc_power_domains()
4991 intel_display_power_put(dev_priv, domain); in modeset_update_crtc_power_domains()
4996 intel_display_set_init_power(dev_priv, false); in modeset_update_crtc_power_domains()
5000 static int valleyview_get_vco(struct drm_i915_private *dev_priv) in valleyview_get_vco() argument
5005 mutex_lock(&dev_priv->dpio_lock); in valleyview_get_vco()
5006 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & in valleyview_get_vco()
5008 mutex_unlock(&dev_priv->dpio_lock); in valleyview_get_vco()
5015 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_update_cdclk() local
5017 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); in vlv_update_cdclk()
5019 dev_priv->vlv_cdclk_freq); in vlv_update_cdclk()
5026 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); in vlv_update_cdclk()
5032 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_set_cdclk() local
5035 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); in valleyview_set_cdclk()
5044 mutex_lock(&dev_priv->rps.hw_lock); in valleyview_set_cdclk()
5045 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in valleyview_set_cdclk()
5048 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); in valleyview_set_cdclk()
5049 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in valleyview_set_cdclk()
5054 mutex_unlock(&dev_priv->rps.hw_lock); in valleyview_set_cdclk()
5059 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in valleyview_set_cdclk()
5061 mutex_lock(&dev_priv->dpio_lock); in valleyview_set_cdclk()
5063 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in valleyview_set_cdclk()
5066 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); in valleyview_set_cdclk()
5068 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in valleyview_set_cdclk()
5072 mutex_unlock(&dev_priv->dpio_lock); in valleyview_set_cdclk()
5075 mutex_lock(&dev_priv->dpio_lock); in valleyview_set_cdclk()
5077 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); in valleyview_set_cdclk()
5088 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); in valleyview_set_cdclk()
5089 mutex_unlock(&dev_priv->dpio_lock); in valleyview_set_cdclk()
5096 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_set_cdclk() local
5099 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); in cherryview_set_cdclk()
5117 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in cherryview_set_cdclk()
5119 mutex_lock(&dev_priv->rps.hw_lock); in cherryview_set_cdclk()
5120 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in cherryview_set_cdclk()
5123 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); in cherryview_set_cdclk()
5124 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in cherryview_set_cdclk()
5129 mutex_unlock(&dev_priv->rps.hw_lock); in cherryview_set_cdclk()
5134 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, in valleyview_calc_cdclk() argument
5137 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; in valleyview_calc_cdclk()
5138 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; in valleyview_calc_cdclk()
5153 if (!IS_CHERRYVIEW(dev_priv) && in valleyview_calc_cdclk()
5165 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) in intel_mode_max_pixclk() argument
5167 struct drm_device *dev = dev_priv->dev; in intel_mode_max_pixclk()
5183 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_modeset_global_pipes() local
5185 int max_pixclk = intel_mode_max_pixclk(dev_priv); in valleyview_modeset_global_pipes()
5187 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == in valleyview_modeset_global_pipes()
5188 dev_priv->vlv_cdclk_freq) in valleyview_modeset_global_pipes()
5197 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) in vlv_program_pfi_credits() argument
5201 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
5206 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { in vlv_program_pfi_credits()
5208 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
5236 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_modeset_global_resources() local
5237 int max_pixclk = intel_mode_max_pixclk(dev_priv); in valleyview_modeset_global_resources()
5238 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); in valleyview_modeset_global_resources()
5240 if (req_cdclk != dev_priv->vlv_cdclk_freq) { in valleyview_modeset_global_resources()
5250 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); in valleyview_modeset_global_resources()
5257 vlv_program_pfi_credits(dev_priv); in valleyview_modeset_global_resources()
5259 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); in valleyview_modeset_global_resources()
5266 struct drm_i915_private *dev_priv = to_i915(dev); in valleyview_crtc_enable() local
5292 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_crtc_enable() local
5302 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in valleyview_crtc_enable()
5335 i9xx_check_fifo_underruns(dev_priv); in valleyview_crtc_enable()
5341 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_set_pll_dividers() local
5350 struct drm_i915_private *dev_priv = to_i915(dev); in i9xx_crtc_enable() local
5372 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in i9xx_crtc_enable()
5403 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); in i9xx_crtc_enable()
5406 i9xx_check_fifo_underruns(dev_priv); in i9xx_crtc_enable()
5412 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pfit_disable() local
5417 assert_pipe_disabled(dev_priv, crtc->pipe); in i9xx_pfit_disable()
5427 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_crtc_disable() local
5442 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in i9xx_crtc_disable()
5453 intel_set_memory_cxsr(dev_priv, false); in i9xx_crtc_disable()
5480 chv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
5482 vlv_disable_pll(dev_priv, pipe); in i9xx_crtc_disable()
5488 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); in i9xx_crtc_disable()
5506 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_control() local
5515 intel_display_power_get(dev_priv, domain); in intel_crtc_control()
5518 dev_priv->display.crtc_enable(crtc); in intel_crtc_control()
5522 dev_priv->display.crtc_disable(crtc); in intel_crtc_control()
5526 intel_display_power_put(dev_priv, domain); in intel_crtc_control()
5551 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_disable() local
5556 dev_priv->display.crtc_disable(crtc); in intel_crtc_disable()
5557 dev_priv->display.off(crtc); in intel_crtc_disable()
5819 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_compute_config() local
5825 dev_priv->display.get_display_clock_speed(dev); in intel_crtc_compute_config()
5880 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_get_display_clock_speed() local
5884 if (dev_priv->hpll_freq == 0) in valleyview_get_display_clock_speed()
5885 dev_priv->hpll_freq = valleyview_get_vco(dev_priv); in valleyview_get_display_clock_speed()
5887 mutex_lock(&dev_priv->dpio_lock); in valleyview_get_display_clock_speed()
5888 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in valleyview_get_display_clock_speed()
5889 mutex_unlock(&dev_priv->dpio_lock); in valleyview_get_display_clock_speed()
5897 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); in valleyview_get_display_clock_speed()
6021 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) in intel_panel_use_ssc() argument
6025 return dev_priv->vbt.lvds_use_ssc in intel_panel_use_ssc()
6026 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); in intel_panel_use_ssc()
6033 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_refclk() local
6041 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { in i9xx_get_refclk()
6042 refclk = dev_priv->vbt.lvds_ssc_freq; in i9xx_get_refclk()
6092 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe in vlv_pllb_recal_opamp() argument
6101 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
6104 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
6106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
6109 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
6111 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
6113 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp()
6115 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
6118 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp()
6125 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pch_transcoder_set_m_n() local
6139 struct drm_i915_private *dev_priv = dev->dev_private; in intel_cpu_transcoder_set_m_n() local
6220 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_prepare_pll() local
6226 mutex_lock(&dev_priv->dpio_lock); in vlv_prepare_pll()
6238 vlv_pllb_recal_opamp(dev_priv, pipe); in vlv_prepare_pll()
6241 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); in vlv_prepare_pll()
6244 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
6246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); in vlv_prepare_pll()
6249 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); in vlv_prepare_pll()
6263 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
6266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); in vlv_prepare_pll()
6272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
6275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), in vlv_prepare_pll()
6281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), in vlv_prepare_pll()
6296 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
6301 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); in vlv_prepare_pll()
6303 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); in vlv_prepare_pll()
6304 mutex_unlock(&dev_priv->dpio_lock); in vlv_prepare_pll()
6324 struct drm_i915_private *dev_priv = dev->dev_private; in chv_prepare_pll() local
6349 mutex_lock(&dev_priv->dpio_lock); in chv_prepare_pll()
6352 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), in chv_prepare_pll()
6359 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); in chv_prepare_pll()
6362 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), in chv_prepare_pll()
6368 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); in chv_prepare_pll()
6371 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); in chv_prepare_pll()
6376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); in chv_prepare_pll()
6379 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); in chv_prepare_pll()
6385 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); in chv_prepare_pll()
6410 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); in chv_prepare_pll()
6412 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); in chv_prepare_pll()
6415 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); in chv_prepare_pll()
6418 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), in chv_prepare_pll()
6419 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | in chv_prepare_pll()
6422 mutex_unlock(&dev_priv->dpio_lock); in chv_prepare_pll()
6479 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_update_pll() local
6535 intel_panel_use_ssc(dev_priv) && num_connectors < 2) in i9xx_update_pll()
6556 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_update_pll() local
6579 intel_panel_use_ssc(dev_priv) && num_connectors < 2) in i8xx_update_pll()
6591 struct drm_i915_private *dev_priv = dev->dev_private; in intel_set_pipe_timings() local
6661 struct drm_i915_private *dev_priv = dev->dev_private; in intel_get_pipe_timings() local
6721 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_set_pipeconf() local
6726 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_set_pipeconf()
6727 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in i9xx_set_pipeconf()
6785 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_crtc_compute_clock() local
6833 ok = dev_priv->display.find_dpll(limit, crtc_state, in i9xx_crtc_compute_clock()
6841 if (is_lvds && dev_priv->lvds_downclock_avail) { in i9xx_crtc_compute_clock()
6849 dev_priv->display.find_dpll(limit, crtc_state, in i9xx_crtc_compute_clock()
6850 dev_priv->lvds_downclock, in i9xx_crtc_compute_clock()
6883 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_pfit_config() local
6913 struct drm_i915_private *dev_priv = dev->dev_private; in vlv_crtc_clock_get() local
6923 mutex_lock(&dev_priv->dpio_lock); in vlv_crtc_clock_get()
6924 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); in vlv_crtc_clock_get()
6925 mutex_unlock(&dev_priv->dpio_lock); in vlv_crtc_clock_get()
6944 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_initial_plane_config() local
7012 struct drm_i915_private *dev_priv = dev->dev_private; in chv_crtc_clock_get() local
7019 mutex_lock(&dev_priv->dpio_lock); in chv_crtc_clock_get()
7020 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); in chv_crtc_clock_get()
7021 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); in chv_crtc_clock_get()
7022 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); in chv_crtc_clock_get()
7023 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); in chv_crtc_clock_get()
7024 mutex_unlock(&dev_priv->dpio_lock); in chv_crtc_clock_get()
7042 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_get_pipe_config() local
7045 if (!intel_display_power_is_enabled(dev_priv, in i9xx_get_pipe_config()
7130 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_init_pch_refclk() local
7157 has_ck505 = dev_priv->vbt.display_clock_mode; in ironlake_init_pch_refclk()
7192 if (intel_panel_use_ssc(dev_priv) && can_ssc) in ironlake_init_pch_refclk()
7196 if (intel_panel_use_ssc(dev_priv) && can_ssc) in ironlake_init_pch_refclk()
7223 if (intel_panel_use_ssc(dev_priv) && can_ssc) { in ironlake_init_pch_refclk()
7238 if (intel_panel_use_ssc(dev_priv) && can_ssc) { in ironlake_init_pch_refclk()
7276 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) in lpt_reset_fdi_mphy() argument
7298 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) in lpt_program_fdi_mphy() argument
7302 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); in lpt_program_fdi_mphy()
7305 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7307 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); in lpt_program_fdi_mphy()
7309 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7311 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); in lpt_program_fdi_mphy()
7313 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7315 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); in lpt_program_fdi_mphy()
7317 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7319 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); in lpt_program_fdi_mphy()
7321 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7323 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); in lpt_program_fdi_mphy()
7326 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7328 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); in lpt_program_fdi_mphy()
7331 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7333 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); in lpt_program_fdi_mphy()
7336 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7338 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); in lpt_program_fdi_mphy()
7341 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7343 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); in lpt_program_fdi_mphy()
7346 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7348 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); in lpt_program_fdi_mphy()
7351 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7353 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); in lpt_program_fdi_mphy()
7355 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7357 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); in lpt_program_fdi_mphy()
7359 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7361 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); in lpt_program_fdi_mphy()
7364 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7366 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); in lpt_program_fdi_mphy()
7369 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); in lpt_program_fdi_mphy()
7381 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_enable_clkout_dp() local
7386 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && in lpt_enable_clkout_dp()
7390 mutex_lock(&dev_priv->dpio_lock); in lpt_enable_clkout_dp()
7392 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); in lpt_enable_clkout_dp()
7395 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_enable_clkout_dp()
7400 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); in lpt_enable_clkout_dp()
7402 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_enable_clkout_dp()
7405 lpt_reset_fdi_mphy(dev_priv); in lpt_enable_clkout_dp()
7406 lpt_program_fdi_mphy(dev_priv); in lpt_enable_clkout_dp()
7410 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? in lpt_enable_clkout_dp()
7412 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); in lpt_enable_clkout_dp()
7414 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); in lpt_enable_clkout_dp()
7416 mutex_unlock(&dev_priv->dpio_lock); in lpt_enable_clkout_dp()
7422 struct drm_i915_private *dev_priv = dev->dev_private; in lpt_disable_clkout_dp() local
7425 mutex_lock(&dev_priv->dpio_lock); in lpt_disable_clkout_dp()
7427 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? in lpt_disable_clkout_dp()
7429 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); in lpt_disable_clkout_dp()
7431 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); in lpt_disable_clkout_dp()
7433 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); in lpt_disable_clkout_dp()
7437 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_disable_clkout_dp()
7441 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); in lpt_disable_clkout_dp()
7444 mutex_unlock(&dev_priv->dpio_lock); in lpt_disable_clkout_dp()
7482 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_refclk() local
7509 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { in ironlake_get_refclk()
7511 dev_priv->vbt.lvds_ssc_freq); in ironlake_get_refclk()
7512 return dev_priv->vbt.lvds_ssc_freq; in ironlake_get_refclk()
7520 struct drm_i915_private *dev_priv = crtc->dev->dev_private; in ironlake_set_pipeconf() local
7570 struct drm_i915_private *dev_priv = dev->dev_private; in intel_set_pipe_csc() local
7627 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_set_pipeconf() local
7684 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_compute_clocks() local
7699 ret = dev_priv->display.find_dpll(limit, crtc_state, in ironlake_compute_clocks()
7705 if (is_lvds && dev_priv->lvds_downclock_avail) { in ironlake_compute_clocks()
7713 dev_priv->display.find_dpll(limit, crtc_state, in ironlake_compute_clocks()
7714 dev_priv->lvds_downclock, in ironlake_compute_clocks()
7745 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_compute_dpll() local
7781 if ((intel_panel_use_ssc(dev_priv) && in ironlake_compute_dpll()
7782 dev_priv->vbt.lvds_ssc_freq == 100000) || in ironlake_compute_dpll()
7829 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) in ironlake_compute_dpll()
7904 struct drm_i915_private *dev_priv = dev->dev_private; in intel_pch_transcoder_get_m_n() local
7922 struct drm_i915_private *dev_priv = dev->dev_private; in intel_cpu_transcoder_get_m_n() local
7980 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_get_pfit_config() local
7997 struct drm_i915_private *dev_priv = dev->dev_private; in skylake_get_initial_plane_config() local
8080 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_pfit_config() local
8105 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_initial_plane_config() local
8173 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_get_pipe_config() local
8176 if (!intel_display_power_is_enabled(dev_priv, in ironlake_get_pipe_config()
8218 if (HAS_PCH_IBX(dev_priv->dev)) { in ironlake_get_pipe_config()
8229 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in ironlake_get_pipe_config()
8231 WARN_ON(!pll->get_hw_state(dev_priv, pll, in ironlake_get_pipe_config()
8251 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) in assert_can_disable_lcpll() argument
8253 struct drm_device *dev = dev_priv->dev; in assert_can_disable_lcpll()
8282 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); in assert_can_disable_lcpll()
8285 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) in hsw_read_dcomp() argument
8287 struct drm_device *dev = dev_priv->dev; in hsw_read_dcomp()
8295 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) in hsw_write_dcomp() argument
8297 struct drm_device *dev = dev_priv->dev; in hsw_write_dcomp()
8300 mutex_lock(&dev_priv->rps.hw_lock); in hsw_write_dcomp()
8301 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, in hsw_write_dcomp()
8304 mutex_unlock(&dev_priv->rps.hw_lock); in hsw_write_dcomp()
8319 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, in hsw_disable_lcpll() argument
8324 assert_can_disable_lcpll(dev_priv); in hsw_disable_lcpll()
8346 val = hsw_read_dcomp(dev_priv); in hsw_disable_lcpll()
8348 hsw_write_dcomp(dev_priv, val); in hsw_disable_lcpll()
8351 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, in hsw_disable_lcpll()
8367 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) in hsw_restore_lcpll() argument
8381 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); in hsw_restore_lcpll()
8389 val = hsw_read_dcomp(dev_priv); in hsw_restore_lcpll()
8392 hsw_write_dcomp(dev_priv, val); in hsw_restore_lcpll()
8411 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); in hsw_restore_lcpll()
8437 void hsw_enable_pc8(struct drm_i915_private *dev_priv) in hsw_enable_pc8() argument
8439 struct drm_device *dev = dev_priv->dev; in hsw_enable_pc8()
8444 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { in hsw_enable_pc8()
8451 hsw_disable_lcpll(dev_priv, true, true); in hsw_enable_pc8()
8454 void hsw_disable_pc8(struct drm_i915_private *dev_priv) in hsw_disable_pc8() argument
8456 struct drm_device *dev = dev_priv->dev; in hsw_disable_pc8()
8461 hsw_restore_lcpll(dev_priv); in hsw_disable_pc8()
8464 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { in hsw_disable_pc8()
8484 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, in skylake_get_ddi_pll() argument
8515 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, in haswell_get_ddi_pll() argument
8535 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_get_ddi_port_state() local
8545 skylake_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
8547 haswell_get_ddi_pll(dev_priv, port, pipe_config); in haswell_get_ddi_port_state()
8550 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; in haswell_get_ddi_port_state()
8552 WARN_ON(!pll->get_hw_state(dev_priv, pll, in haswell_get_ddi_port_state()
8577 struct drm_i915_private *dev_priv = dev->dev_private; in haswell_get_pipe_config() local
8581 if (!intel_display_power_is_enabled(dev_priv, in haswell_get_pipe_config()
8610 if (!intel_display_power_is_enabled(dev_priv, in haswell_get_pipe_config()
8623 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { in haswell_get_pipe_config()
8647 struct drm_i915_private *dev_priv = dev->dev_private; in i845_update_cursor() local
8709 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_update_cursor() local
8758 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_update_cursor() local
8952 struct drm_i915_private *dev_priv = dev->dev_private; in mode_fits_in_fbdev() local
8956 if (!dev_priv->fbdev) in mode_fits_in_fbdev()
8959 if (!dev_priv->fbdev->fb) in mode_fits_in_fbdev()
8962 obj = dev_priv->fbdev->fb->obj; in mode_fits_in_fbdev()
8965 fb = &dev_priv->fbdev->fb->base; in mode_fits_in_fbdev()
9206 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pll_refclk() local
9210 return dev_priv->vbt.lvds_ssc_freq; in i9xx_pll_refclk()
9224 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_crtc_clock_get() local
9350 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_mode_get() local
9397 struct drm_i915_private *dev_priv = dev->dev_private; in intel_decrease_pllclock() local
9403 if (!dev_priv->lvds_downclock_avail) in intel_decrease_pllclock()
9417 assert_panel_unlocked(dev_priv, pipe); in intel_decrease_pllclock()
9432 struct drm_i915_private *dev_priv = dev->dev_private; in intel_mark_busy() local
9434 if (dev_priv->mm.busy) in intel_mark_busy()
9437 intel_runtime_pm_get(dev_priv); in intel_mark_busy()
9438 i915_update_gfx_val(dev_priv); in intel_mark_busy()
9440 gen6_rps_busy(dev_priv); in intel_mark_busy()
9441 dev_priv->mm.busy = true; in intel_mark_busy()
9446 struct drm_i915_private *dev_priv = dev->dev_private; in intel_mark_idle() local
9449 if (!dev_priv->mm.busy) in intel_mark_idle()
9452 dev_priv->mm.busy = false; in intel_mark_idle()
9464 intel_runtime_pm_put(dev_priv); in intel_mark_idle()
9556 struct drm_i915_private *dev_priv = dev->dev_private; in intel_finish_page_flip() local
9557 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_finish_page_flip()
9564 struct drm_i915_private *dev_priv = dev->dev_private; in intel_finish_page_flip_plane() local
9565 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; in intel_finish_page_flip_plane()
9579 struct drm_i915_private *dev_priv = dev->dev_private; in page_flip_finished() local
9581 if (i915_reset_in_progress(&dev_priv->gpu_error) || in page_flip_finished()
9582 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) in page_flip_finished()
9618 struct drm_i915_private *dev_priv = dev->dev_private; in intel_prepare_page_flip() local
9620 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); in intel_prepare_page_flip()
9721 struct drm_i915_private *dev_priv = dev->dev_private; in intel_gen4_queue_flip() local
9760 struct drm_i915_private *dev_priv = dev->dev_private; in intel_gen6_queue_flip() local
9914 struct drm_i915_private *dev_priv = dev->dev_private; in skl_do_mmio_flip() local
9948 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_do_mmio_flip() local
10045 struct drm_i915_private *dev_priv = dev->dev_private; in __intel_pageflip_stall_check() local
10083 struct drm_i915_private *dev_priv = dev->dev_private; in intel_check_page_flip() local
10084 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in intel_check_page_flip()
10108 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_page_flip() local
10139 if (i915_terminally_wedged(&dev_priv->gpu_error)) in intel_crtc_page_flip()
10177 flush_workqueue(dev_priv->wq); in intel_crtc_page_flip()
10193 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); in intel_crtc_page_flip()
10199 ring = &dev_priv->ring[BCS]; in intel_crtc_page_flip()
10204 ring = &dev_priv->ring[BCS]; in intel_crtc_page_flip()
10208 ring = &dev_priv->ring[BCS]; in intel_crtc_page_flip()
10210 ring = &dev_priv->ring[RCS]; in intel_crtc_page_flip()
10230 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, in intel_crtc_page_flip()
10869 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_update_state() local
10874 intel_shared_dpll_commit(dev_priv); in intel_modeset_update_state()
11134 struct drm_i915_private *dev_priv = dev->dev_private; in check_wm_state() local
11142 skl_ddb_get_hw_state(dev_priv, &hw_ddb); in check_wm_state()
11143 sw_ddb = &dev_priv->wm.skl_hw.ddb; in check_wm_state()
11153 for_each_plane(dev_priv, pipe, plane) { in check_wm_state()
11257 struct drm_i915_private *dev_priv = dev->dev_private; in check_crtc_state() local
11290 active = dev_priv->display.get_pipe_config(crtc, in check_crtc_state()
11294 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in check_crtc_state()
11295 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) in check_crtc_state()
11324 struct drm_i915_private *dev_priv = dev->dev_private; in check_shared_dpll_state() local
11329 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in check_shared_dpll_state()
11330 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in check_shared_dpll_state()
11338 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); in check_shared_dpll_state()
11486 struct drm_i915_private *dev_priv = to_i915(dev); in __intel_set_mode_setup_plls() local
11491 if (!dev_priv->display.crtc_compute_clock) in __intel_set_mode_setup_plls()
11494 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); in __intel_set_mode_setup_plls()
11500 ret = dev_priv->display.crtc_compute_clock(intel_crtc, in __intel_set_mode_setup_plls()
11503 intel_shared_dpll_abort_config(dev_priv); in __intel_set_mode_setup_plls()
11521 struct drm_i915_private *dev_priv = dev->dev_private; in __intel_set_mode() local
11565 dev_priv->display.crtc_disable(&intel_crtc->base); in __intel_set_mode()
11615 dev_priv->display.crtc_enable(&intel_crtc->base); in __intel_set_mode()
12240 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, in ibx_pch_dpll_get_hw_state() argument
12246 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) in ibx_pch_dpll_get_hw_state()
12257 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, in ibx_pch_dpll_mode_set() argument
12264 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, in ibx_pch_dpll_enable() argument
12268 ibx_assert_pch_refclk_enabled(dev_priv); in ibx_pch_dpll_enable()
12286 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, in ibx_pch_dpll_disable() argument
12289 struct drm_device *dev = dev_priv->dev; in ibx_pch_dpll_disable()
12295 assert_pch_transcoder_disabled(dev_priv, crtc->pipe); in ibx_pch_dpll_disable()
12310 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_pch_dpll_init() local
12313 dev_priv->num_shared_dpll = 2; in ibx_pch_dpll_init()
12315 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in ibx_pch_dpll_init()
12316 dev_priv->shared_dplls[i].id = i; in ibx_pch_dpll_init()
12317 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; in ibx_pch_dpll_init()
12318 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; in ibx_pch_dpll_init()
12319 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; in ibx_pch_dpll_init()
12320 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; in ibx_pch_dpll_init()
12321 dev_priv->shared_dplls[i].get_hw_state = in ibx_pch_dpll_init()
12328 struct drm_i915_private *dev_priv = dev->dev_private; in intel_shared_dpll_init() local
12335 dev_priv->num_shared_dpll = 0; in intel_shared_dpll_init()
12337 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); in intel_shared_dpll_init()
12453 struct drm_i915_private *dev_priv = dev->dev_private; in intel_check_primary_plane() local
12488 dev_priv->fbc.crtc == intel_crtc && in intel_check_primary_plane()
12532 struct drm_i915_private *dev_priv = dev->dev_private; in intel_commit_primary_plane() local
12550 dev_priv->display.update_primary_plane(crtc, plane->fb, in intel_commit_primary_plane()
12568 struct drm_i915_private *dev_priv = dev->dev_private; in intel_begin_crtc_commit() local
12613 intel_runtime_pm_get(dev_priv); in intel_begin_crtc_commit()
12625 struct drm_i915_private *dev_priv = dev->dev_private; in intel_finish_crtc_commit() local
12633 intel_runtime_pm_put(dev_priv); in intel_finish_crtc_commit()
12886 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crtc_init() local
12938 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || in intel_crtc_init()
12939 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); in intel_crtc_init()
12940 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; in intel_crtc_init()
12941 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; in intel_crtc_init()
13011 struct drm_i915_private *dev_priv = dev->dev_private; in has_edp_a() local
13027 struct drm_i915_private *dev_priv = dev->dev_private; in intel_crt_present() local
13038 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) in intel_crt_present()
13046 struct drm_i915_private *dev_priv = dev->dev_private; in intel_setup_outputs() local
13427 struct drm_i915_private *dev_priv = dev->dev_private; in intel_init_display() local
13430 dev_priv->display.find_dpll = g4x_find_best_dpll; in intel_init_display()
13432 dev_priv->display.find_dpll = chv_find_best_dpll; in intel_init_display()
13434 dev_priv->display.find_dpll = vlv_find_best_dpll; in intel_init_display()
13436 dev_priv->display.find_dpll = pnv_find_best_dpll; in intel_init_display()
13438 dev_priv->display.find_dpll = i9xx_find_best_dpll; in intel_init_display()
13441 dev_priv->display.get_pipe_config = haswell_get_pipe_config; in intel_init_display()
13442 dev_priv->display.get_initial_plane_config = in intel_init_display()
13444 dev_priv->display.crtc_compute_clock = in intel_init_display()
13446 dev_priv->display.crtc_enable = haswell_crtc_enable; in intel_init_display()
13447 dev_priv->display.crtc_disable = haswell_crtc_disable; in intel_init_display()
13448 dev_priv->display.off = ironlake_crtc_off; in intel_init_display()
13449 dev_priv->display.update_primary_plane = in intel_init_display()
13452 dev_priv->display.get_pipe_config = haswell_get_pipe_config; in intel_init_display()
13453 dev_priv->display.get_initial_plane_config = in intel_init_display()
13455 dev_priv->display.crtc_compute_clock = in intel_init_display()
13457 dev_priv->display.crtc_enable = haswell_crtc_enable; in intel_init_display()
13458 dev_priv->display.crtc_disable = haswell_crtc_disable; in intel_init_display()
13459 dev_priv->display.off = ironlake_crtc_off; in intel_init_display()
13460 dev_priv->display.update_primary_plane = in intel_init_display()
13463 dev_priv->display.get_pipe_config = ironlake_get_pipe_config; in intel_init_display()
13464 dev_priv->display.get_initial_plane_config = in intel_init_display()
13466 dev_priv->display.crtc_compute_clock = in intel_init_display()
13468 dev_priv->display.crtc_enable = ironlake_crtc_enable; in intel_init_display()
13469 dev_priv->display.crtc_disable = ironlake_crtc_disable; in intel_init_display()
13470 dev_priv->display.off = ironlake_crtc_off; in intel_init_display()
13471 dev_priv->display.update_primary_plane = in intel_init_display()
13474 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display()
13475 dev_priv->display.get_initial_plane_config = in intel_init_display()
13477 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; in intel_init_display()
13478 dev_priv->display.crtc_enable = valleyview_crtc_enable; in intel_init_display()
13479 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display()
13480 dev_priv->display.off = i9xx_crtc_off; in intel_init_display()
13481 dev_priv->display.update_primary_plane = in intel_init_display()
13484 dev_priv->display.get_pipe_config = i9xx_get_pipe_config; in intel_init_display()
13485 dev_priv->display.get_initial_plane_config = in intel_init_display()
13487 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; in intel_init_display()
13488 dev_priv->display.crtc_enable = i9xx_crtc_enable; in intel_init_display()
13489 dev_priv->display.crtc_disable = i9xx_crtc_disable; in intel_init_display()
13490 dev_priv->display.off = i9xx_crtc_off; in intel_init_display()
13491 dev_priv->display.update_primary_plane = in intel_init_display()
13497 dev_priv->display.get_display_clock_speed = in intel_init_display()
13500 dev_priv->display.get_display_clock_speed = in intel_init_display()
13503 dev_priv->display.get_display_clock_speed = in intel_init_display()
13506 dev_priv->display.get_display_clock_speed = in intel_init_display()
13509 dev_priv->display.get_display_clock_speed = in intel_init_display()
13512 dev_priv->display.get_display_clock_speed = in intel_init_display()
13515 dev_priv->display.get_display_clock_speed = in intel_init_display()
13518 dev_priv->display.get_display_clock_speed = in intel_init_display()
13521 dev_priv->display.get_display_clock_speed = in intel_init_display()
13525 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; in intel_init_display()
13527 dev_priv->display.fdi_link_train = gen6_fdi_link_train; in intel_init_display()
13530 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; in intel_init_display()
13532 dev_priv->display.fdi_link_train = hsw_fdi_link_train; in intel_init_display()
13534 dev_priv->display.modeset_global_resources = in intel_init_display()
13540 dev_priv->display.queue_flip = intel_gen2_queue_flip; in intel_init_display()
13544 dev_priv->display.queue_flip = intel_gen3_queue_flip; in intel_init_display()
13549 dev_priv->display.queue_flip = intel_gen4_queue_flip; in intel_init_display()
13553 dev_priv->display.queue_flip = intel_gen6_queue_flip; in intel_init_display()
13557 dev_priv->display.queue_flip = intel_gen7_queue_flip; in intel_init_display()
13563 dev_priv->display.queue_flip = intel_default_queue_flip; in intel_init_display()
13568 mutex_init(&dev_priv->pps_mutex); in intel_init_display()
13578 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_pipea_force() local
13580 dev_priv->quirks |= QUIRK_PIPEA_FORCE; in quirk_pipea_force()
13586 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_pipeb_force() local
13588 dev_priv->quirks |= QUIRK_PIPEB_FORCE; in quirk_pipeb_force()
13597 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_ssc_force_disable() local
13598 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; in quirk_ssc_force_disable()
13608 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_invert_brightness() local
13609 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; in quirk_invert_brightness()
13616 struct drm_i915_private *dev_priv = dev->dev_private; in quirk_backlight_present() local
13617 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; in quirk_backlight_present()
13736 struct drm_i915_private *dev_priv = dev->dev_private; in i915_disable_vga() local
13766 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_init() local
13800 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { in intel_modeset_init()
13803 dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); in intel_modeset_init()
13804 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; in intel_modeset_init()
13833 dev->mode_config.fb_base = dev_priv->gtt.mappable_base; in intel_modeset_init()
13839 for_each_pipe(dev_priv, pipe) { in intel_modeset_init()
13841 for_each_sprite(dev_priv, pipe, sprite) { in intel_modeset_init()
13875 if (dev_priv->display.get_initial_plane_config) { in intel_modeset_init()
13876 dev_priv->display.get_initial_plane_config(crtc, in intel_modeset_init()
13915 struct drm_i915_private *dev_priv = dev->dev_private; in intel_check_plane_mapping() local
13934 struct drm_i915_private *dev_priv = dev->dev_private; in intel_sanitize_crtc() local
13964 dev_priv->display.crtc_disable(&crtc->base); in intel_sanitize_crtc()
13988 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && in intel_sanitize_crtc()
14094 struct drm_i915_private *dev_priv = dev->dev_private; in i915_redisable_vga_power_on() local
14105 struct drm_i915_private *dev_priv = dev->dev_private; in i915_redisable_vga() local
14114 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) in i915_redisable_vga()
14122 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in primary_get_hw_state() local
14132 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_readout_hw_state() local
14144 crtc->active = dev_priv->display.get_pipe_config(crtc, in intel_modeset_readout_hw_state()
14156 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_modeset_readout_hw_state()
14157 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_readout_hw_state()
14159 pll->on = pll->get_hw_state(dev_priv, pll, in intel_modeset_readout_hw_state()
14174 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); in intel_modeset_readout_hw_state()
14181 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_readout_hw_state()
14217 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_setup_hw_state() local
14245 for_each_pipe(dev_priv, pipe) { in intel_modeset_setup_hw_state()
14246 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in intel_modeset_setup_hw_state()
14254 for (i = 0; i < dev_priv->num_shared_dpll; i++) { in intel_modeset_setup_hw_state()
14255 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; in intel_modeset_setup_hw_state()
14262 pll->disable(dev_priv, pll); in intel_modeset_setup_hw_state()
14278 for_each_pipe(dev_priv, pipe) { in intel_modeset_setup_hw_state()
14280 dev_priv->pipe_to_crtc_mapping[pipe]; in intel_modeset_setup_hw_state()
14343 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_cleanup() local
14355 intel_irq_uninstall(dev_priv); in intel_modeset_cleanup()
14412 struct drm_i915_private *dev_priv = dev->dev_private; in intel_modeset_vga_set_state() local
14416 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { in intel_modeset_vga_set_state()
14429 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { in intel_modeset_vga_set_state()
14484 struct drm_i915_private *dev_priv = dev->dev_private; in intel_display_capture_error_state() local
14504 for_each_pipe(dev_priv, i) { in intel_display_capture_error_state()
14506 __intel_display_power_is_enabled(dev_priv, in intel_display_capture_error_state()
14535 if (HAS_DDI(dev_priv->dev)) in intel_display_capture_error_state()
14542 __intel_display_power_is_enabled(dev_priv, in intel_display_capture_error_state()
14568 struct drm_i915_private *dev_priv = dev->dev_private; in intel_display_print_error_state() local
14578 for_each_pipe(dev_priv, i) { in intel_display_print_error_state()