Lines Matching refs:adjusted_mode
974 intel_crtc->config->base.adjusted_mode.crtc_clock; in intel_crtc_active()
3202 const struct drm_display_mode *adjusted_mode; in intel_update_pipe_size() local
3221 adjusted_mode = &crtc->config->base.adjusted_mode; in intel_update_pipe_size()
3224 ((adjusted_mode->crtc_hdisplay - 1) << 16) | in intel_update_pipe_size()
3225 (adjusted_mode->crtc_vdisplay - 1)); in intel_update_pipe_size()
3233 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; in intel_update_pipe_size()
3234 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; in intel_update_pipe_size()
3825 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; in lpt_program_iclkip()
5174 intel_crtc->new_config->base.adjusted_mode.crtc_clock); in intel_mode_max_pixclk()
5765 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in ironlake_fdi_compute_config() local
5779 fdi_dotclock = adjusted_mode->crtc_clock; in ironlake_fdi_compute_config()
5820 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_crtc_compute_config() local
5835 adjusted_mode->crtc_clock > clock_limit * 9 / 10) { in intel_crtc_compute_config()
5840 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) in intel_crtc_compute_config()
5858 adjusted_mode->hsync_start == adjusted_mode->hdisplay) in intel_crtc_compute_config()
6594 struct drm_display_mode *adjusted_mode = in intel_set_pipe_timings() local
6595 &intel_crtc->config->base.adjusted_mode; in intel_set_pipe_timings()
6601 crtc_vtotal = adjusted_mode->crtc_vtotal; in intel_set_pipe_timings()
6602 crtc_vblank_end = adjusted_mode->crtc_vblank_end; in intel_set_pipe_timings()
6604 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_set_pipe_timings()
6610 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; in intel_set_pipe_timings()
6612 vsyncshift = adjusted_mode->crtc_hsync_start - in intel_set_pipe_timings()
6613 adjusted_mode->crtc_htotal / 2; in intel_set_pipe_timings()
6615 vsyncshift += adjusted_mode->crtc_htotal; in intel_set_pipe_timings()
6622 (adjusted_mode->crtc_hdisplay - 1) | in intel_set_pipe_timings()
6623 ((adjusted_mode->crtc_htotal - 1) << 16)); in intel_set_pipe_timings()
6625 (adjusted_mode->crtc_hblank_start - 1) | in intel_set_pipe_timings()
6626 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in intel_set_pipe_timings()
6628 (adjusted_mode->crtc_hsync_start - 1) | in intel_set_pipe_timings()
6629 ((adjusted_mode->crtc_hsync_end - 1) << 16)); in intel_set_pipe_timings()
6632 (adjusted_mode->crtc_vdisplay - 1) | in intel_set_pipe_timings()
6635 (adjusted_mode->crtc_vblank_start - 1) | in intel_set_pipe_timings()
6638 (adjusted_mode->crtc_vsync_start - 1) | in intel_set_pipe_timings()
6639 ((adjusted_mode->crtc_vsync_end - 1) << 16)); in intel_set_pipe_timings()
6666 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
6667 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
6669 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
6670 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
6672 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
6673 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
6676 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
6677 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
6679 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
6680 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
6682 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; in intel_get_pipe_timings()
6683 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; in intel_get_pipe_timings()
6686 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; in intel_get_pipe_timings()
6687 pipe_config->base.adjusted_mode.crtc_vtotal += 1; in intel_get_pipe_timings()
6688 pipe_config->base.adjusted_mode.crtc_vblank_end += 1; in intel_get_pipe_timings()
6702 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; in intel_mode_from_pipe_config()
6703 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; in intel_mode_from_pipe_config()
6704 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; in intel_mode_from_pipe_config()
6705 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; in intel_mode_from_pipe_config()
6707 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; in intel_mode_from_pipe_config()
6708 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; in intel_mode_from_pipe_config()
6709 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; in intel_mode_from_pipe_config()
6710 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; in intel_mode_from_pipe_config()
6712 mode->flags = pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
6714 mode->clock = pipe_config->base.adjusted_mode.crtc_clock; in intel_mode_from_pipe_config()
6715 mode->flags |= pipe_config->base.adjusted_mode.flags; in intel_mode_from_pipe_config()
6765 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { in i9xx_set_pipeconf()
7548 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in ironlake_set_pipeconf()
7638 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) in haswell_set_pipeconf()
9341 pipe_config->base.adjusted_mode.crtc_clock = in ironlake_pch_clock_get()
10521 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
10522 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); in intel_dump_pipe_config()
10663 drm_mode_copy(&pipe_config->base.adjusted_mode, mode); in intel_modeset_pipe_config()
10675 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
10677 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; in intel_modeset_pipe_config()
10679 if (!(pipe_config->base.adjusted_mode.flags & in intel_modeset_pipe_config()
10681 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; in intel_modeset_pipe_config()
10710 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, in intel_modeset_pipe_config()
10737 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock in intel_modeset_pipe_config()
11036 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); in intel_pipe_config_compare()
11037 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); in intel_pipe_config_compare()
11038 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); in intel_pipe_config_compare()
11039 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); in intel_pipe_config_compare()
11040 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); in intel_pipe_config_compare()
11041 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); in intel_pipe_config_compare()
11043 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); in intel_pipe_config_compare()
11044 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); in intel_pipe_config_compare()
11045 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); in intel_pipe_config_compare()
11046 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); in intel_pipe_config_compare()
11047 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); in intel_pipe_config_compare()
11048 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); in intel_pipe_config_compare()
11059 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
11063 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
11065 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
11067 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
11069 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, in intel_pipe_config_compare()
11119 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); in intel_pipe_config_compare()
11387 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), in ironlake_check_encoder_dotclock()
11389 pipe_config->base.adjusted_mode.crtc_clock, dotclock); in ironlake_check_encoder_dotclock()
11415 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; in update_scanline_offset()
11587 &pipe_config->base.adjusted_mode); in __intel_set_mode()