2825 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))  in ironlake_update_primary_plane()
2858 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))  in ironlake_update_primary_plane()
2870 		if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {  in ironlake_update_primary_plane()
2887 	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {  in ironlake_update_primary_plane()
4280 		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))  in ironlake_pfit_enable()
4423 	if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&  in intel_crtc_load_lut()
5719 	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {  in ironlake_check_fdi_lanes()
6645 	if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&  in intel_set_pipe_timings()
7635 	if (IS_HASWELL(dev) && intel_crtc->config->dither)  in haswell_set_pipeconf()
8138 	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {  in ironlake_get_initial_plane_config()
8267 	if (IS_HASWELL(dev))  in assert_can_disable_lcpll()
8289 	if (IS_HASWELL(dev))  in hsw_read_dcomp()
8299 	if (IS_HASWELL(dev)) {  in hsw_write_dcomp()
8630 	if (IS_HASWELL(dev))  in haswell_get_pipe_config()
8733 		if (IS_HASWELL(dev) || IS_BROADWELL(dev))  in i9xx_update_cursor()
10203 	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {  in intel_crtc_page_flip()
11052 	if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||  in intel_pipe_config_compare()
11099 	if (IS_HASWELL(dev))  in intel_pipe_config_compare()
13531 	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {  in intel_init_display()
14501 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))  in intel_display_capture_error_state()
14521 		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))  in intel_display_capture_error_state()
14575 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))  in intel_display_print_error_state()
14592 		if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))  in intel_display_print_error_state()