468 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {  in intel_ironlake_limit()
492 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {  in intel_g4x_limit()
519 		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))  in intel_limit()
528 		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))  in intel_limit()
533 		if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))  in intel_limit()
632 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {  in i9xx_find_best_dpll()
695 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {  in pnv_find_best_dpll()
760 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {  in g4x_find_best_dpll()
3227 	    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||  in intel_update_pipe_size()
5850 	if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&  in intel_crtc_compute_config()
6040 	} else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&  in i9xx_get_refclk()
6083 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&  in i9xx_update_pll_dividers()
6491 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))  in i9xx_update_pll()
6534 	else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&  in i9xx_update_pll()
6564 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {  in i8xx_update_pll()
6578 	if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&  in i8xx_update_pll()
6807 		case INTEL_OUTPUT_LVDS:  in i9xx_crtc_compute_clock()
7142 		case INTEL_OUTPUT_LVDS:  in ironlake_init_pch_refclk()
7500 		case INTEL_OUTPUT_LVDS:  in ironlake_get_refclk()
7689 	is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);  in ironlake_compute_clocks()
7764 		case INTEL_OUTPUT_LVDS:  in ironlake_compute_dpll()
7847 	is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);  in ironlake_crtc_compute_clock()