1600 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1607 	I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);  in vlv_enable_pll()
1611 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1614 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1617 	I915_WRITE(reg, dpll);  in vlv_enable_pll()
1648 	I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);  in chv_enable_pll()
1655 	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);  in chv_enable_pll()
1698 		I915_WRITE(DPLL(!crtc->pipe),  in i9xx_enable_pll()
1702 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1709 		I915_WRITE(DPLL_MD(crtc->pipe),  in i9xx_enable_pll()
1717 		I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1721 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1724 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1727 	I915_WRITE(reg, dpll);  in i9xx_enable_pll()
1751 		I915_WRITE(DPLL(PIPE_B),  in i9xx_disable_pll()
1753 		I915_WRITE(DPLL(PIPE_A),  in i9xx_disable_pll()
1765 	I915_WRITE(DPLL(pipe), 0);  in i9xx_disable_pll()
1782 	I915_WRITE(DPLL(pipe), val);  in vlv_disable_pll()
1799 	I915_WRITE(DPLL(pipe), val);  in chv_disable_pll()
1968 		I915_WRITE(reg, val);  in ironlake_enable_pch_transcoder()
1994 	I915_WRITE(reg, val | TRANS_ENABLE);  in ironlake_enable_pch_transcoder()
2014 	I915_WRITE(_TRANSA_CHICKEN2, val);  in lpt_enable_pch_transcoder()
2025 	I915_WRITE(LPT_TRANSCONF, val);  in lpt_enable_pch_transcoder()
2046 	I915_WRITE(reg, val);  in ironlake_disable_pch_transcoder()
2056 		I915_WRITE(reg, val);  in ironlake_disable_pch_transcoder()
2066 	I915_WRITE(LPT_TRANSCONF, val);  in lpt_disable_pch_transcoder()
2074 	I915_WRITE(_TRANSA_CHICKEN2, val);  in lpt_disable_pch_transcoder()
2132 	I915_WRITE(reg, val | PIPECONF_ENABLE);  in intel_enable_pipe()
2179 	I915_WRITE(reg, val);  in intel_disable_pipe()
2194 	I915_WRITE(reg, I915_READ(reg));  in intel_flush_primary_plane()
2680 		I915_WRITE(reg, 0);  in i9xx_update_primary_plane()
2682 			I915_WRITE(DSPSURF(plane), 0);  in i9xx_update_primary_plane()
2684 			I915_WRITE(DSPADDR(plane), 0);  in i9xx_update_primary_plane()
2706 		I915_WRITE(DSPSIZE(plane),  in i9xx_update_primary_plane()
2709 		I915_WRITE(DSPPOS(plane), 0);  in i9xx_update_primary_plane()
2711 		I915_WRITE(PRIMSIZE(plane),  in i9xx_update_primary_plane()
2714 		I915_WRITE(PRIMPOS(plane), 0);  in i9xx_update_primary_plane()
2715 		I915_WRITE(PRIMCNSTALPHA(plane), 0);  in i9xx_update_primary_plane()
2781 	I915_WRITE(reg, dspcntr);  in i9xx_update_primary_plane()
2783 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);  in i9xx_update_primary_plane()
2785 		I915_WRITE(DSPSURF(plane),  in i9xx_update_primary_plane()
2787 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);  in i9xx_update_primary_plane()
2788 		I915_WRITE(DSPLINOFF(plane), linear_offset);  in i9xx_update_primary_plane()
2790 		I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);  in i9xx_update_primary_plane()
2809 		I915_WRITE(reg, 0);  in ironlake_update_primary_plane()
2810 		I915_WRITE(DSPSURF(plane), 0);  in ironlake_update_primary_plane()
2882 	I915_WRITE(reg, dspcntr);  in ironlake_update_primary_plane()
2884 	I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);  in ironlake_update_primary_plane()
2885 	I915_WRITE(DSPSURF(plane),  in ironlake_update_primary_plane()
2888 		I915_WRITE(DSPOFFSET(plane), (y << 16) | x);  in ironlake_update_primary_plane()
2890 		I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);  in ironlake_update_primary_plane()
2891 		I915_WRITE(DSPLINOFF(plane), linear_offset);  in ironlake_update_primary_plane()
2954 		I915_WRITE(PLANE_CTL(pipe, 0), 0);  in skylake_update_primary_plane()
2955 		I915_WRITE(PLANE_SURF(pipe, 0), 0);  in skylake_update_primary_plane()
3020 	I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);  in skylake_update_primary_plane()
3021 	I915_WRITE(PLANE_POS(pipe, 0), 0);  in skylake_update_primary_plane()
3022 	I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);  in skylake_update_primary_plane()
3023 	I915_WRITE(PLANE_SIZE(pipe, 0),  in skylake_update_primary_plane()
3026 	I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);  in skylake_update_primary_plane()
3027 	I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);  in skylake_update_primary_plane()
3223 	I915_WRITE(PIPESRC(crtc->pipe),  in intel_update_pipe_size()
3229 		I915_WRITE(PF_CTL(crtc->pipe), 0);  in intel_update_pipe_size()
3230 		I915_WRITE(PF_WIN_POS(crtc->pipe), 0);  in intel_update_pipe_size()
3231 		I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);  in intel_update_pipe_size()
3255 	I915_WRITE(reg, temp);  in intel_fdi_normal_train()
3266 	I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);  in intel_fdi_normal_train()
3274 		I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |  in intel_fdi_normal_train()
3296 	I915_WRITE(reg, temp);  in ironlake_fdi_link_train()
3307 	I915_WRITE(reg, temp | FDI_TX_ENABLE);  in ironlake_fdi_link_train()
3313 	I915_WRITE(reg, temp | FDI_RX_ENABLE);  in ironlake_fdi_link_train()
3319 	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);  in ironlake_fdi_link_train()
3320 	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |  in ironlake_fdi_link_train()
3330 			I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);  in ironlake_fdi_link_train()
3342 	I915_WRITE(reg, temp);  in ironlake_fdi_link_train()
3348 	I915_WRITE(reg, temp);  in ironlake_fdi_link_train()
3359 			I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);  in ironlake_fdi_link_train()
3393 	I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3408 	I915_WRITE(reg, temp | FDI_TX_ENABLE);  in gen6_fdi_link_train()
3410 	I915_WRITE(FDI_RX_MISC(pipe),  in gen6_fdi_link_train()
3422 	I915_WRITE(reg, temp | FDI_RX_ENABLE);  in gen6_fdi_link_train()
3432 		I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3442 				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);  in gen6_fdi_link_train()
3464 	I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3475 	I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3485 		I915_WRITE(reg, temp);  in gen6_fdi_link_train()
3495 				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);  in gen6_fdi_link_train()
3525 	I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3540 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3547 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3558 		I915_WRITE(reg, temp | FDI_TX_ENABLE);  in ivb_manual_fdi_link_train()
3560 		I915_WRITE(FDI_RX_MISC(pipe),  in ivb_manual_fdi_link_train()
3567 		I915_WRITE(reg, temp | FDI_RX_ENABLE);  in ivb_manual_fdi_link_train()
3579 				I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);  in ivb_manual_fdi_link_train()
3596 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3602 		I915_WRITE(reg, temp);  in ivb_manual_fdi_link_train()
3614 				I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);  in ivb_manual_fdi_link_train()
3643 	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);  in ironlake_fdi_pll_enable()
3650 	I915_WRITE(reg, temp | FDI_PCDCLK);  in ironlake_fdi_pll_enable()
3659 		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);  in ironlake_fdi_pll_enable()
3676 	I915_WRITE(reg, temp & ~FDI_PCDCLK);  in ironlake_fdi_pll_disable()
3681 	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);  in ironlake_fdi_pll_disable()
3688 	I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);  in ironlake_fdi_pll_disable()
3706 	I915_WRITE(reg, temp & ~FDI_TX_ENABLE);  in ironlake_fdi_disable()
3713 	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);  in ironlake_fdi_disable()
3720 		I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);  in ironlake_fdi_disable()
3727 	I915_WRITE(reg, temp);  in ironlake_fdi_disable()
3741 	I915_WRITE(reg, temp);  in ironlake_fdi_disable()
3834 	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);  in lpt_program_iclkip()
3904 	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);  in lpt_program_iclkip()
3916 	I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
3918 	I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
3920 	I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
3923 	I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
3925 	I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
3927 	I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
3929 	I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),  in ironlake_pch_transcoder_set_timings()
3950 	I915_WRITE(SOUTH_CHICKEN1, temp);  in cpt_set_fdi_bc_bifurcation()
4000 	I915_WRITE(FDI_RX_TUSIZE1(pipe),  in ironlake_pch_enable()
4018 		I915_WRITE(PCH_DPLL_SEL, temp);  in ironlake_pch_enable()
4067 		I915_WRITE(reg, temp);  in ironlake_pch_enable()
4263 		I915_WRITE(PS_CTL(pipe), PS_ENABLE);  in skylake_pfit_enable()
4264 		I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);  in skylake_pfit_enable()
4265 		I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);  in skylake_pfit_enable()
4281 			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |  in ironlake_pfit_enable()
4284 			I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);  in ironlake_pfit_enable()
4285 		I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);  in ironlake_pfit_enable()
4286 		I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);  in ironlake_pfit_enable()
4358 		I915_WRITE(IPS_CTL, IPS_ENABLE);  in hsw_enable_ips()
4386 		I915_WRITE(IPS_CTL, 0);  in hsw_disable_ips()
4431 		I915_WRITE(palreg + 4 * i,  in intel_crtc_load_lut()
4641 		I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),  in haswell_crtc_enable()
4715 		I915_WRITE(PS_CTL(pipe), 0);  in skylake_pfit_disable()
4716 		I915_WRITE(PS_WIN_POS(pipe), 0);  in skylake_pfit_disable()
4717 		I915_WRITE(PS_WIN_SZ(pipe), 0);  in skylake_pfit_disable()
4730 		I915_WRITE(PF_CTL(pipe), 0);  in ironlake_pfit_disable()
4731 		I915_WRITE(PF_WIN_POS(pipe), 0);  in ironlake_pfit_disable()
4732 		I915_WRITE(PF_WIN_SZ(pipe), 0);  in ironlake_pfit_disable()
4779 			I915_WRITE(reg, temp);  in ironlake_crtc_disable()
4784 			I915_WRITE(PCH_DPLL_SEL, temp);  in ironlake_crtc_disable()
4882 	I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);  in i9xx_pfit_enable()
4883 	I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);  in i9xx_pfit_enable()
4887 	I915_WRITE(BCLRPAT(crtc->pipe), 0);  in i9xx_pfit_enable()
5026 	I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));  in vlv_update_cdclk()
5220 	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |  in vlv_program_pfi_credits()
5223 	I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |  in vlv_program_pfi_credits()
5294 		I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);  in valleyview_crtc_enable()
5295 		I915_WRITE(CHV_CANVAS(pipe), 0);  in valleyview_crtc_enable()
5343 	I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);  in i9xx_set_pll_dividers()
5344 	I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);  in i9xx_set_pll_dividers()
5421 	I915_WRITE(PFIT_CONTROL, 0);  in i9xx_pfit_disable()
6128 	I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_pch_transcoder_set_m_n()
6129 	I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);  in intel_pch_transcoder_set_m_n()
6130 	I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);  in intel_pch_transcoder_set_m_n()
6131 	I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);  in intel_pch_transcoder_set_m_n()
6144 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_cpu_transcoder_set_m_n()
6145 		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);  in intel_cpu_transcoder_set_m_n()
6146 		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);  in intel_cpu_transcoder_set_m_n()
6147 		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);  in intel_cpu_transcoder_set_m_n()
6154 			I915_WRITE(PIPE_DATA_M2(transcoder),  in intel_cpu_transcoder_set_m_n()
6156 			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);  in intel_cpu_transcoder_set_m_n()
6157 			I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);  in intel_cpu_transcoder_set_m_n()
6158 			I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);  in intel_cpu_transcoder_set_m_n()
6161 		I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_cpu_transcoder_set_m_n()
6162 		I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);  in intel_cpu_transcoder_set_m_n()
6163 		I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);  in intel_cpu_transcoder_set_m_n()
6164 		I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);  in intel_cpu_transcoder_set_m_n()
6346 	I915_WRITE(dpll_reg,  in chv_prepare_pll()
6619 		I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);  in intel_set_pipe_timings()
6621 	I915_WRITE(HTOTAL(cpu_transcoder),  in intel_set_pipe_timings()
6624 	I915_WRITE(HBLANK(cpu_transcoder),  in intel_set_pipe_timings()
6627 	I915_WRITE(HSYNC(cpu_transcoder),  in intel_set_pipe_timings()
6631 	I915_WRITE(VTOTAL(cpu_transcoder),  in intel_set_pipe_timings()
6634 	I915_WRITE(VBLANK(cpu_transcoder),  in intel_set_pipe_timings()
6637 	I915_WRITE(VSYNC(cpu_transcoder),  in intel_set_pipe_timings()
6647 		I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));  in intel_set_pipe_timings()
6652 	I915_WRITE(PIPESRC(pipe),  in intel_set_pipe_timings()
6777 	I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);  in i9xx_set_pipeconf()
7230 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
7246 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
7257 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
7268 		I915_WRITE(PCH_DREF_CONTROL, val);  in ironlake_init_pch_refclk()
7282 	I915_WRITE(SOUTH_CHICKEN2, tmp);  in lpt_reset_fdi_mphy()
7290 	I915_WRITE(SOUTH_CHICKEN2, tmp);  in lpt_reset_fdi_mphy()
7556 	I915_WRITE(PIPECONF(pipe), val);  in ironlake_set_pipeconf()
7590 	I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);  in intel_set_pipe_csc()
7591 	I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);  in intel_set_pipe_csc()
7593 	I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);  in intel_set_pipe_csc()
7594 	I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);  in intel_set_pipe_csc()
7596 	I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);  in intel_set_pipe_csc()
7597 	I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);  in intel_set_pipe_csc()
7599 	I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);  in intel_set_pipe_csc()
7600 	I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);  in intel_set_pipe_csc()
7601 	I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);  in intel_set_pipe_csc()
7609 		I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);  in intel_set_pipe_csc()
7610 		I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);  in intel_set_pipe_csc()
7611 		I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);  in intel_set_pipe_csc()
7613 		I915_WRITE(PIPE_CSC_MODE(pipe), 0);  in intel_set_pipe_csc()
7620 		I915_WRITE(PIPE_CSC_MODE(pipe), mode);  in intel_set_pipe_csc()
7643 	I915_WRITE(PIPECONF(cpu_transcoder), val);  in haswell_set_pipeconf()
7646 	I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);  in haswell_set_pipeconf()
7673 		I915_WRITE(PIPEMISC(pipe), val);  in haswell_set_pipeconf()
8306 		I915_WRITE(D_COMP_BDW, val);  in hsw_write_dcomp()
8330 		I915_WRITE(LCPLL_CTL, val);  in hsw_disable_lcpll()
8340 	I915_WRITE(LCPLL_CTL, val);  in hsw_disable_lcpll()
8358 		I915_WRITE(LCPLL_CTL, val);  in hsw_disable_lcpll()
8385 		I915_WRITE(LCPLL_CTL, val);  in hsw_restore_lcpll()
8396 	I915_WRITE(LCPLL_CTL, val);  in hsw_restore_lcpll()
8404 		I915_WRITE(LCPLL_CTL, val);  in hsw_restore_lcpll()
8447 		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);  in hsw_enable_pc8()
8467 		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);  in hsw_disable_pc8()
8684 		I915_WRITE(_CURACNTR, 0);  in i845_update_cursor()
8690 		I915_WRITE(_CURABASE, base);  in i845_update_cursor()
8695 		I915_WRITE(CURSIZE, size);  in i845_update_cursor()
8700 		I915_WRITE(_CURACNTR, cntl);  in i845_update_cursor()
8741 		I915_WRITE(CURCNTR(pipe), cntl);  in i9xx_update_cursor()
8747 	I915_WRITE(CURBASE(pipe), base);  in i9xx_update_cursor()
8795 	I915_WRITE(CURPOS(pipe), pos);  in intel_crtc_update_cursor()
9421 		I915_WRITE(dpll_reg, dpll);  in intel_decrease_pllclock()
9938 	I915_WRITE(PLANE_CTL(pipe, 0), ctl);  in skl_do_mmio_flip()
9939 	I915_WRITE(PLANE_STRIDE(pipe, 0), stride);  in skl_do_mmio_flip()
9941 	I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);  in skl_do_mmio_flip()
9963 	I915_WRITE(reg, dspcntr);  in ilk_do_mmio_flip()
9965 	I915_WRITE(DSPSURF(intel_crtc->plane),  in ilk_do_mmio_flip()
12260 	I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);  in ibx_pch_dpll_mode_set()
12261 	I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);  in ibx_pch_dpll_mode_set()
12270 	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);  in ibx_pch_dpll_enable()
12281 	I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);  in ibx_pch_dpll_enable()
12298 	I915_WRITE(PCH_DPLL(pll->id), 0);  in ibx_pch_dpll_disable()
13748 	I915_WRITE(vga_reg, VGA_DISP_DISABLE);  in i915_disable_vga()
13939 	I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);  in intel_sanitize_crtc()