Lines Matching refs:DPLL
1100 reg = DPLL(pipe); in assert_pll()
1588 int reg = DPLL(crtc->pipe); in vlv_enable_pll()
1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll()
1677 int reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1698 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1751 I915_WRITE(DPLL(PIPE_B), in i9xx_disable_pll()
1752 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1753 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll()
1754 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1765 I915_WRITE(DPLL(pipe), 0); in i9xx_disable_pll()
1766 POSTING_READ(DPLL(pipe)); in i9xx_disable_pll()
1782 I915_WRITE(DPLL(pipe), val); in vlv_disable_pll()
1783 POSTING_READ(DPLL(pipe)); in vlv_disable_pll()
1799 I915_WRITE(DPLL(pipe), val); in chv_disable_pll()
1800 POSTING_READ(DPLL(pipe)); in chv_disable_pll()
1832 dpll_reg = DPLL(0); in vlv_wait_port_ready()
1836 dpll_reg = DPLL(0); in vlv_wait_port_ready()
6326 int dpll_reg = DPLL(crtc->pipe); in chv_prepare_pll()
7089 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
7099 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
9374 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()
9412 int dpll_reg = DPLL(pipe); in intel_decrease_pllclock()