Lines Matching refs:link_clock
776 int link_clock = 0; in skl_ddi_clock_get() local
784 link_clock = skl_calc_wrpll_link(dev_priv, dpll); in skl_ddi_clock_get()
786 link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll); in skl_ddi_clock_get()
787 link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll); in skl_ddi_clock_get()
789 switch (link_clock) { in skl_ddi_clock_get()
791 link_clock = 81000; in skl_ddi_clock_get()
794 link_clock = 108000; in skl_ddi_clock_get()
797 link_clock = 135000; in skl_ddi_clock_get()
800 link_clock = 162000; in skl_ddi_clock_get()
803 link_clock = 216000; in skl_ddi_clock_get()
806 link_clock = 270000; in skl_ddi_clock_get()
812 link_clock *= 2; in skl_ddi_clock_get()
815 pipe_config->port_clock = link_clock; in skl_ddi_clock_get()
829 int link_clock = 0; in hsw_ddi_clock_get() local
835 link_clock = 81000; in hsw_ddi_clock_get()
838 link_clock = 135000; in hsw_ddi_clock_get()
841 link_clock = 270000; in hsw_ddi_clock_get()
844 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); in hsw_ddi_clock_get()
847 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); in hsw_ddi_clock_get()
852 link_clock = 81000; in hsw_ddi_clock_get()
854 link_clock = 135000; in hsw_ddi_clock_get()
856 link_clock = 270000; in hsw_ddi_clock_get()
867 pipe_config->port_clock = link_clock * 2; in hsw_ddi_clock_get()