Lines Matching refs:u8
34 u8 signature[20]; /**< Always starts with 'VBT$' */
38 u8 vbt_checksum;
39 u8 reserved0;
45 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */
53 u8 type; /* 0 == desktop, 1 == mobile */
54 u8 relstage;
55 u8 chipset;
56 u8 lvds_present:1;
57 u8 tv_present:1;
58 u8 rsvd2:6; /* finish byte */
59 u8 rsvd3[4];
60 u8 signon[155];
61 u8 copyright[61];
63 u8 dos_boot_mode;
64 u8 bandwidth_percent;
65 u8 rsvd4; /* popup memory size */
66 u8 resize_pci_bios;
67 u8 rsvd5; /* is crt already on ddc2 */
113 u8 panel_fitting:2;
114 u8 flexaim:1;
115 u8 msg_enable:1;
116 u8 clear_screen:3;
117 u8 color_flip:1;
120 u8 download_ext_vbt:1;
121 u8 enable_ssc:1;
122 u8 ssc_freq:1;
123 u8 enable_lfp_on_override:1;
124 u8 disable_ssc_ddt:1;
125 u8 rsvd7:1;
126 u8 display_clock_mode:1;
127 u8 rsvd8:1; /* finish byte */
130 u8 disable_smooth_vision:1;
131 u8 single_dvi:1;
132 u8 rsvd9:1;
133 u8 fdi_rx_polarity_inverted:1;
134 u8 rsvd10:4; /* finish byte */
137 u8 legacy_monitor_detect;
140 u8 int_crt_support:1;
141 u8 int_tv_support:1;
142 u8 int_efp_support:1;
143 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */
144 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */
145 u8 rsvd11:3; /* finish byte */
212 u8 device_id[10]; /* ascii string */
214 u8 dvo_port; /* See Device_PORT_* above */
215 u8 i2c_pin;
216 u8 slave_addr;
217 u8 ddc_pin;
219 u8 dvo_cfg; /* See DEVICE_CFG_* above */
220 u8 dvo2_port;
221 u8 i2c2_pin;
222 u8 slave2_addr;
223 u8 ddc2_pin;
224 u8 capabilities;
225 u8 dvo_wiring;/* See DEVICE_WIRE_* above */
226 u8 dvo2_wiring;
228 u8 dvo_function;
237 u8 not_common1[12];
238 u8 dvo_port;
239 u8 not_common2[2];
240 u8 ddc_pin;
249 u8 raw[33];
259 u8 crt_ddc_gmbus_pin;
262 u8 dpms_acpi:1;
263 u8 skip_boot_crt_detect:1;
264 u8 dpms_aim:1;
265 u8 rsvd1:5; /* finish byte */
268 u8 boot_display[2];
269 u8 child_dev_size;
289 u8 panel_type;
290 u8 rsvd1;
292 u8 pfit_mode:2;
293 u8 pfit_text_mode_enhanced:1;
294 u8 pfit_gfx_mode_enhanced:1;
295 u8 pfit_ratio_auto:1;
296 u8 pixel_dither:1;
297 u8 lvds_edid:1;
298 u8 rsvd2:1;
299 u8 rsvd4;
317 u8 fp_table_size;
319 u8 dvo_table_size;
321 u8 pnp_table_size;
325 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */
348 u8 hactive_lo;
349 u8 hblank_lo;
350 u8 hblank_hi:4;
351 u8 hactive_hi:4;
352 u8 vactive_lo;
353 u8 vblank_lo;
354 u8 vblank_hi:4;
355 u8 vactive_hi:4;
356 u8 hsync_off_lo;
357 u8 hsync_pulse_width;
358 u8 vsync_pulse_width:4;
359 u8 vsync_off:4;
360 u8 rsvd0:6;
361 u8 hsync_off_hi:2;
362 u8 h_image;
363 u8 v_image;
364 u8 max_hv;
365 u8 h_border;
366 u8 v_border;
367 u8 rsvd1:3;
368 u8 digital:2;
369 u8 vsync_positive:1;
370 u8 hsync_positive:1;
371 u8 rsvd2:1;
378 u8 mfg_week;
379 u8 mfg_year;
396 u8 type:2;
397 u8 active_low_pwm:1;
398 u8 obsolete1:5;
400 u8 min_brightness;
401 u8 obsolete2;
402 u8 obsolete3;
406 u8 entry_size;
408 u8 level[16];
420 u8 aimdb_id;
426 u8 fp_timing_size;
428 u8 dvo_timing_size;
430 u8 text_fitting_size;
432 u8 graphics_fitting_size;
441 u8 panel_backlight;
442 u8 h40_set_panel_type;
443 u8 panel_type;
444 u8 ssc_clk_freq;
447 u8 sclalarcoeff_tab_row_num;
448 u8 sclalarcoeff_tab_row_size;
449 u8 coefficient[8];
450 u8 panel_misc_bits_1;
451 u8 panel_misc_bits_2;
452 u8 panel_misc_bits_3;
453 u8 panel_misc_bits_4;
463 u8 boot_dev_algorithm:1;
464 u8 block_display_switch:1;
465 u8 allow_display_switch:1;
466 u8 hotplug_dvo:1;
467 u8 dual_view_zoom:1;
468 u8 int15h_hook:1;
469 u8 sprite_in_clone:1;
470 u8 primary_lfp_id:1;
474 u8 boot_mode_bpp;
475 u8 boot_mode_refresh;
492 u8 static_display:1;
493 u8 reserved2:7;
496 u8 legacy_crt_max_refresh;
498 u8 hdmi_termination;
499 u8 custom_vbt_version;
542 u8 rate:4;
543 u8 lanes:4;
544 u8 preemphasis:4;
545 u8 vswing:4;
562 u8 full_link:1;
563 u8 require_aux_to_wakeup:1;
564 u8 feature_bits_rsvd:6;
567 u8 idle_frames:4;
568 u8 lines_to_wait:3;
569 u8 wait_times_rsvd:1;
827 u8 rsvd5;
835 u8 byte_clk_sel:2;
837 u8 rsvd6:6;
868 u8 tclk_miss;
869 u8 tclk_post;
870 u8 rsvd12;
871 u8 tclk_pre;
872 u8 tclk_prepare;
873 u8 tclk_settle;
874 u8 tclk_term_enable;
875 u8 tclk_trail;
877 u8 rsvd13;
878 u8 td_term_enable;
879 u8 teot;
880 u8 ths_exit;
881 u8 ths_prepare;
883 u8 rsvd14;
884 u8 ths_settle;
885 u8 ths_skip;
886 u8 ths_trail;
887 u8 tinit;
888 u8 tlpx;
889 u8 rsvd15[3];
892 u8 panel_enable;
893 u8 bl_enable;
894 u8 pwm_enable;
895 u8 reset_r_n;
896 u8 pwr_down_r;
897 u8 stdby_r_n;
925 u8 version;
926 u8 data[0];