Lines Matching defs:mipi_config
781 struct mipi_config { struct
782 u16 panel_id;
785 u32 enable_dithering:1;
786 u32 rsvd1:1;
787 u32 is_bridge:1;
789 u32 panel_arch_type:2;
790 u32 is_cmd_mode:1;
795 u32 video_transfer_mode:2;
797 u32 cabc_supported:1;
798 u32 pwm_blc:1;
805 u32 videomode_color_format:4;
812 u32 rotation:2;
813 u32 bta_enabled:1;
814 u32 rsvd2:15;
820 u16 dual_link:2;
821 u16 lane_cnt:2;
822 u16 pixel_overlap:3;
823 u16 rsvd3:9;
825 u16 rsvd4;
827 u8 rsvd5;
828 u32 target_burst_mode_freq;
829 u32 dsi_ddr_clk;
830 u32 bridge_ref_clk;
835 u8 byte_clk_sel:2;
837 u8 rsvd6:6;
840 u16 dphy_param_valid:1;
841 u16 eot_pkt_disabled:1;
842 u16 enable_clk_stop:1;
843 u16 rsvd7:13;
845 u32 hs_tx_timeout;
846 u32 lp_rx_timeout;
847 u32 turn_around_timeout;
848 u32 device_reset_timer;
849 u32 master_init_timer;
850 u32 dbi_bw_timer;
851 u32 lp_byte_clk_val;
854 u32 prepare_cnt:6;
855 u32 rsvd8:2;
856 u32 clk_zero_cnt:8;
857 u32 trail_cnt:5;
858 u32 rsvd9:3;
859 u32 exit_zero_cnt:6;
860 u32 rsvd10:2;
862 u32 clk_lane_switch_cnt;
863 u32 hl_switch_cnt;
865 u32 rsvd11[6];
868 u8 tclk_miss;
869 u8 tclk_post;
870 u8 rsvd12;
871 u8 tclk_pre;
872 u8 tclk_prepare;
873 u8 tclk_settle;
874 u8 tclk_term_enable;
875 u8 tclk_trail;
876 u16 tclk_prepare_clkzero;
877 u8 rsvd13;
878 u8 td_term_enable;
902 * 6 * bdb_mipi_config, followed by 6 pps data argument
916 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; argument