311 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_act_freq_mhz_show()
315 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
330 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
345 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_cur_freq_mhz_show()
349 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
350 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);  in gt_cur_freq_mhz_show()
351 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
367 			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in vlv_rpe_freq_mhz_show()
377 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_show()
379 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
380 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_show()
381 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
400 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_store()
402 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
406 	if (val < dev_priv->rps.min_freq ||  in gt_max_freq_mhz_store()
407 	    val > dev_priv->rps.max_freq ||  in gt_max_freq_mhz_store()
408 	    val < dev_priv->rps.min_freq_softlimit) {  in gt_max_freq_mhz_store()
409 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
413 	if (val > dev_priv->rps.rp0_freq)  in gt_max_freq_mhz_store()
417 	dev_priv->rps.max_freq_softlimit = val;  in gt_max_freq_mhz_store()
419 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_max_freq_mhz_store()
420 		      dev_priv->rps.min_freq_softlimit,  in gt_max_freq_mhz_store()
421 		      dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_store()
428 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
440 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_show()
442 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
443 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);  in gt_min_freq_mhz_show()
444 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
463 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_store()
465 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
469 	if (val < dev_priv->rps.min_freq ||  in gt_min_freq_mhz_store()
470 	    val > dev_priv->rps.max_freq ||  in gt_min_freq_mhz_store()
471 	    val > dev_priv->rps.max_freq_softlimit) {  in gt_min_freq_mhz_store()
472 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
476 	dev_priv->rps.min_freq_softlimit = val;  in gt_min_freq_mhz_store()
478 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_min_freq_mhz_store()
479 		      dev_priv->rps.min_freq_softlimit,  in gt_min_freq_mhz_store()
480 		      dev_priv->rps.max_freq_softlimit);  in gt_min_freq_mhz_store()
487 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
514 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);  in gt_rp_mhz_show()
516 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);  in gt_rp_mhz_show()
518 		val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);  in gt_rp_mhz_show()