40 	struct drm_i915_private *dev_priv = dev->dev_private;  in calc_residency()  local
48 	intel_runtime_pm_get(dev_priv);  in calc_residency()
95 	intel_runtime_pm_put(dev_priv);  in calc_residency()
199 	struct drm_i915_private *dev_priv = drm_dev->dev_private;  in i915_l3_read()  local
215 	if (dev_priv->l3_parity.remap_info[slice])  in i915_l3_read()
217 		       dev_priv->l3_parity.remap_info[slice] + (offset/4),  in i915_l3_read()
235 	struct drm_i915_private *dev_priv = drm_dev->dev_private;  in i915_l3_write()  local
252 	if (!dev_priv->l3_parity.remap_info[slice]) {  in i915_l3_write()
272 		dev_priv->l3_parity.remap_info[slice] = temp;  in i915_l3_write()
274 	memcpy(dev_priv->l3_parity.remap_info[slice] + (offset/4), buf, count);  in i915_l3_write()
277 	list_for_each_entry(ctx, &dev_priv->context_list, link)  in i915_l3_write()
308 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_act_freq_mhz_show()  local
311 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_act_freq_mhz_show()
313 	intel_runtime_pm_get(dev_priv);  in gt_act_freq_mhz_show()
315 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
316 	if (IS_VALLEYVIEW(dev_priv->dev)) {  in gt_act_freq_mhz_show()
318 		freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);  in gt_act_freq_mhz_show()
319 		ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);  in gt_act_freq_mhz_show()
322 		if (IS_GEN9(dev_priv))  in gt_act_freq_mhz_show()
324 		else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in gt_act_freq_mhz_show()
328 		ret = intel_gpu_freq(dev_priv, ret);  in gt_act_freq_mhz_show()
330 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_act_freq_mhz_show()
332 	intel_runtime_pm_put(dev_priv);  in gt_act_freq_mhz_show()
342 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_cur_freq_mhz_show()  local
345 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_cur_freq_mhz_show()
347 	intel_runtime_pm_get(dev_priv);  in gt_cur_freq_mhz_show()
349 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
350 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq);  in gt_cur_freq_mhz_show()
351 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_cur_freq_mhz_show()
353 	intel_runtime_pm_put(dev_priv);  in gt_cur_freq_mhz_show()
363 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_rpe_freq_mhz_show()  local
367 			intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in vlv_rpe_freq_mhz_show()
374 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_max_freq_mhz_show()  local
377 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_show()
379 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
380 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_show()
381 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_show()
392 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_max_freq_mhz_store()  local
400 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_max_freq_mhz_store()
402 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
404 	val = intel_freq_opcode(dev_priv, val);  in gt_max_freq_mhz_store()
406 	if (val < dev_priv->rps.min_freq ||  in gt_max_freq_mhz_store()
407 	    val > dev_priv->rps.max_freq ||  in gt_max_freq_mhz_store()
408 	    val < dev_priv->rps.min_freq_softlimit) {  in gt_max_freq_mhz_store()
409 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
413 	if (val > dev_priv->rps.rp0_freq)  in gt_max_freq_mhz_store()
415 			  intel_gpu_freq(dev_priv, val));  in gt_max_freq_mhz_store()
417 	dev_priv->rps.max_freq_softlimit = val;  in gt_max_freq_mhz_store()
419 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_max_freq_mhz_store()
420 		      dev_priv->rps.min_freq_softlimit,  in gt_max_freq_mhz_store()
421 		      dev_priv->rps.max_freq_softlimit);  in gt_max_freq_mhz_store()
428 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_max_freq_mhz_store()
437 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_min_freq_mhz_show()  local
440 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_show()
442 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
443 	ret = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);  in gt_min_freq_mhz_show()
444 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_show()
455 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_min_freq_mhz_store()  local
463 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in gt_min_freq_mhz_store()
465 	mutex_lock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
467 	val = intel_freq_opcode(dev_priv, val);  in gt_min_freq_mhz_store()
469 	if (val < dev_priv->rps.min_freq ||  in gt_min_freq_mhz_store()
470 	    val > dev_priv->rps.max_freq ||  in gt_min_freq_mhz_store()
471 	    val > dev_priv->rps.max_freq_softlimit) {  in gt_min_freq_mhz_store()
472 		mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
476 	dev_priv->rps.min_freq_softlimit = val;  in gt_min_freq_mhz_store()
478 	val = clamp_t(int, dev_priv->rps.cur_freq,  in gt_min_freq_mhz_store()
479 		      dev_priv->rps.min_freq_softlimit,  in gt_min_freq_mhz_store()
480 		      dev_priv->rps.max_freq_softlimit);  in gt_min_freq_mhz_store()
487 	mutex_unlock(&dev_priv->rps.hw_lock);  in gt_min_freq_mhz_store()
510 	struct drm_i915_private *dev_priv = dev->dev_private;  in gt_rp_mhz_show()  local
514 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp0_freq);  in gt_rp_mhz_show()
516 		val = intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq);  in gt_rp_mhz_show()
518 		val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq);  in gt_rp_mhz_show()