Lines Matching refs:display_mmio_offset

1836 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
1837 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
1838 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
1924 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
1925 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
1926 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
1996 #define DSPCLK_GATE_D	(dev_priv->info.display_mmio_offset + 0x6200)
2136 		       dev_priv->info.display_mmio_offset)
2645 	dev_priv->info.display_mmio_offset)
2808 #define PORT_HOTPLUG_EN		(dev_priv->info.display_mmio_offset + 0x61110)
2838 #define PORT_HOTPLUG_STAT	(dev_priv->info.display_mmio_offset + 0x61114)
2915 #define PORT_DFT2_G4X		(dev_priv->info.display_mmio_offset + 0x61154)
3125 #define PFIT_CONTROL	(dev_priv->info.display_mmio_offset + 0x61230)
3143 #define PFIT_PGM_RATIOS	(dev_priv->info.display_mmio_offset + 0x61234)
3155 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3157 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3158 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3162 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3163 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3167 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3168 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3173 #define BLC_PWM_CTL2	(dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3196 #define BLC_PWM_CTL	(dev_priv->info.display_mmio_offset + 0x61254)
3218 #define BLC_HIST_CTL	(dev_priv->info.display_mmio_offset + 0x61260)
4036 	dev_priv->info.display_mmio_offset)
4107 #define DSPARB			(dev_priv->info.display_mmio_offset + 0x70030)
4119 #define DSPFW1			(dev_priv->info.display_mmio_offset + 0x70034)
4130 #define DSPFW2			(dev_priv->info.display_mmio_offset + 0x70038)
4146 #define DSPFW3			(dev_priv->info.display_mmio_offset + 0x7003c)
4454 	dev_priv->info.display_mmio_offset)
4548 #define SWF00			(dev_priv->info.display_mmio_offset + 0x71410)
4549 #define SWF01			(dev_priv->info.display_mmio_offset + 0x71414)
4550 #define SWF02			(dev_priv->info.display_mmio_offset + 0x71418)
4551 #define SWF03			(dev_priv->info.display_mmio_offset + 0x7141c)
4552 #define SWF04			(dev_priv->info.display_mmio_offset + 0x71420)
4553 #define SWF05			(dev_priv->info.display_mmio_offset + 0x71424)
4554 #define SWF06			(dev_priv->info.display_mmio_offset + 0x71428)
4555 #define SWF10			(dev_priv->info.display_mmio_offset + 0x70410)
4556 #define SWF11			(dev_priv->info.display_mmio_offset + 0x70414)
4557 #define SWF14			(dev_priv->info.display_mmio_offset + 0x71420)
4558 #define SWF30			(dev_priv->info.display_mmio_offset + 0x72414)
4559 #define SWF31			(dev_priv->info.display_mmio_offset + 0x72418)
4560 #define SWF32			(dev_priv->info.display_mmio_offset + 0x7241c)
4563 #define _PIPEBDSL		(dev_priv->info.display_mmio_offset + 0x71000)
4564 #define _PIPEBCONF		(dev_priv->info.display_mmio_offset + 0x71008)
4565 #define _PIPEBSTAT		(dev_priv->info.display_mmio_offset + 0x71024)
4568 #define _PIPEB_FRMCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71040)
4569 #define _PIPEB_FLIPCOUNT_GM45	(dev_priv->info.display_mmio_offset + 0x71044)
4573 #define _DSPBCNTR		(dev_priv->info.display_mmio_offset + 0x71180)
4578 #define _DSPBADDR		(dev_priv->info.display_mmio_offset + 0x71184)
4579 #define _DSPBSTRIDE		(dev_priv->info.display_mmio_offset + 0x71188)
4580 #define _DSPBPOS		(dev_priv->info.display_mmio_offset + 0x7118C)
4581 #define _DSPBSIZE		(dev_priv->info.display_mmio_offset + 0x71190)
4582 #define _DSPBSURF		(dev_priv->info.display_mmio_offset + 0x7119C)
4583 #define _DSPBTILEOFF		(dev_priv->info.display_mmio_offset + 0x711A4)
4584 #define _DSPBOFFSET		(dev_priv->info.display_mmio_offset + 0x711A4)
4585 #define _DSPBSURFLIVE		(dev_priv->info.display_mmio_offset + 0x711AC)
6355 #define G4X_AUD_VID_DID			(dev_priv->info.display_mmio_offset + 0x62020)
7332 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
7333 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)