Lines Matching refs:dev_priv
810 #define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
1836 #define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
1837 #define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
1838 #define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030)
1924 #define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
1925 #define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
1926 #define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c)
1996 #define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
2135 #define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
2136 dev_priv->info.display_mmio_offset)
2464 #define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \ argument
2643 #define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2644 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2645 dev_priv->info.display_mmio_offset)
2808 #define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
2838 #define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
2915 #define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154)
3125 #define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
3143 #define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
3155 #define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
3157 #define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
3158 #define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
3162 #define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
3163 #define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
3167 #define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
3168 #define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
3173 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
3196 #define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
3218 #define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
4034 #define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
4035 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4036 dev_priv->info.display_mmio_offset)
4107 #define DSPARB (dev_priv->info.display_mmio_offset + 0x70030)
4119 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
4130 #define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
4146 #define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
4452 #define _CURSOR2(pipe, reg) (dev_priv->info.cursor_offsets[(pipe)] - \
4453 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
4454 dev_priv->info.display_mmio_offset)
4548 #define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
4549 #define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
4550 #define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
4551 #define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
4552 #define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
4553 #define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
4554 #define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
4555 #define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
4556 #define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
4557 #define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
4558 #define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
4559 #define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
4560 #define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
4563 #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
4564 #define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
4565 #define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
4568 #define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
4569 #define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
4573 #define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
4578 #define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
4579 #define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
4580 #define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
4581 #define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
4582 #define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
4583 #define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
4584 #define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
4585 #define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
6355 #define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
6929 #define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
6930 #define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
6940 #define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
6941 #define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
6944 #define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
6945 #define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
6981 #define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
6982 #define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
7005 #define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
7006 #define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
7011 #define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
7012 #define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
7017 #define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
7018 #define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
7023 #define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
7024 #define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
7029 #define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
7030 #define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
7038 #define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
7039 #define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
7047 #define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
7048 #define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
7052 #define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
7053 #define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
7057 #define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
7058 #define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
7062 #define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
7063 #define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
7067 #define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
7068 #define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
7072 #define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
7073 #define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
7077 #define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
7078 #define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
7082 #define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
7083 #define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
7089 #define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
7090 #define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
7101 #define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
7102 #define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
7108 #define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
7109 #define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
7115 #define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
7116 #define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
7122 #define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
7123 #define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
7133 #define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
7134 #define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
7146 #define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
7147 #define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
7154 #define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
7155 #define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
7160 #define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
7161 #define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
7165 #define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
7166 #define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
7169 #define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
7170 #define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
7183 #define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
7184 #define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
7202 #define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
7203 #define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
7210 #define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
7211 #define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
7224 #define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
7225 #define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
7229 #define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7231 #define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base \
7240 #define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
7241 #define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
7247 #define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
7248 #define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
7251 #define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
7252 #define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
7258 #define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
7272 #define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
7273 #define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
7287 #define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
7288 #define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
7295 #define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
7296 #define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
7302 #define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
7303 #define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
7312 #define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
7313 #define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
7319 #define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
7320 #define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
7325 #define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
7326 #define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
7332 #define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
7333 #define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)