Lines Matching refs:pipe
366 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_enable_pipestat() argument
369 u32 reg = PIPESTAT(pipe); in __i915_enable_pipestat()
378 pipe_name(pipe), enable_mask, status_mask)) in __i915_enable_pipestat()
384 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in __i915_enable_pipestat()
393 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_disable_pipestat() argument
396 u32 reg = PIPESTAT(pipe); in __i915_disable_pipestat()
405 pipe_name(pipe), enable_mask, status_mask)) in __i915_disable_pipestat()
411 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in __i915_disable_pipestat()
447 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_enable_pipestat() argument
457 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_enable_pipestat()
461 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_disable_pipestat() argument
471 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_disable_pipestat()
544 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) in i8xx_get_vblank_counter() argument
553 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) in i915_get_vblank_counter() argument
560 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in i915_get_vblank_counter()
576 high_frame = PIPEFRAME(pipe); in i915_get_vblank_counter()
577 low_frame = PIPEFRAMEPIXEL(pipe); in i915_get_vblank_counter()
602 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) in gm45_get_vblank_counter() argument
605 int reg = PIPE_FRMCOUNT_GM45(pipe); in gm45_get_vblank_counter()
618 enum pipe pipe = crtc->pipe; in __intel_get_crtc_scanline() local
626 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()
628 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
637 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, in i915_get_crtc_scanoutpos() argument
642 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in i915_get_crtc_scanoutpos()
653 "pipe %c\n", pipe_name(pipe)); in i915_get_crtc_scanoutpos()
694 …position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHI… in i915_get_crtc_scanoutpos()
774 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, in i915_get_vblank_timestamp() argument
781 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { in i915_get_vblank_timestamp()
782 DRM_ERROR("Invalid crtc %d\n", pipe); in i915_get_vblank_timestamp()
787 crtc = intel_get_crtc_for_pipe(dev, pipe); in i915_get_vblank_timestamp()
789 DRM_ERROR("Invalid crtc %d\n", pipe); in i915_get_vblank_timestamp()
794 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); in i915_get_vblank_timestamp()
799 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, in i915_get_vblank_timestamp()
1542 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, in display_pipe_crc_irq_handler() argument
1548 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; in display_pipe_crc_irq_handler()
1571 entry->frame = dev->driver->get_vblank_counter(dev, pipe); in display_pipe_crc_irq_handler()
1587 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, in display_pipe_crc_irq_handler() argument
1594 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in hsw_pipe_crc_irq_handler() argument
1598 display_pipe_crc_irq_handler(dev, pipe, in hsw_pipe_crc_irq_handler()
1599 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in hsw_pipe_crc_irq_handler()
1603 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in ivb_pipe_crc_irq_handler() argument
1607 display_pipe_crc_irq_handler(dev, pipe, in ivb_pipe_crc_irq_handler()
1608 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1609 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1610 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1611 I915_READ(PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
1612 I915_READ(PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
1615 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) in i9xx_pipe_crc_irq_handler() argument
1621 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); in i9xx_pipe_crc_irq_handler()
1626 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); in i9xx_pipe_crc_irq_handler()
1630 display_pipe_crc_irq_handler(dev, pipe, in i9xx_pipe_crc_irq_handler()
1631 I915_READ(PIPE_CRC_RES_RED(pipe)), in i9xx_pipe_crc_irq_handler()
1632 I915_READ(PIPE_CRC_RES_GREEN(pipe)), in i9xx_pipe_crc_irq_handler()
1633 I915_READ(PIPE_CRC_RES_BLUE(pipe)), in i9xx_pipe_crc_irq_handler()
1664 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) in intel_pipe_handle_vblank() argument
1666 if (!drm_handle_vblank(dev, pipe)) in intel_pipe_handle_vblank()
1676 int pipe; in valleyview_pipestat_irq_handler() local
1679 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1694 switch (pipe) { in valleyview_pipestat_irq_handler()
1706 mask |= dev_priv->pipestat_irq_mask[pipe]; in valleyview_pipestat_irq_handler()
1711 reg = PIPESTAT(pipe); in valleyview_pipestat_irq_handler()
1713 pipe_stats[pipe] = I915_READ(reg) & mask; in valleyview_pipestat_irq_handler()
1718 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | in valleyview_pipestat_irq_handler()
1720 I915_WRITE(reg, pipe_stats[pipe]); in valleyview_pipestat_irq_handler()
1724 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1725 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && in valleyview_pipestat_irq_handler()
1726 intel_pipe_handle_vblank(dev, pipe)) in valleyview_pipestat_irq_handler()
1727 intel_check_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1729 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { in valleyview_pipestat_irq_handler()
1730 intel_prepare_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1731 intel_finish_page_flip(dev, pipe); in valleyview_pipestat_irq_handler()
1734 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
1735 i9xx_pipe_crc_irq_handler(dev, pipe); in valleyview_pipestat_irq_handler()
1737 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
1738 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1867 int pipe; in ibx_irq_handler() local
1899 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
1901 pipe_name(pipe), in ibx_irq_handler()
1902 I915_READ(FDI_RX_IIR(pipe))); in ibx_irq_handler()
1921 enum pipe pipe; in ivb_err_int_handler() local
1926 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
1927 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) in ivb_err_int_handler()
1928 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1930 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { in ivb_err_int_handler()
1932 ivb_pipe_crc_irq_handler(dev, pipe); in ivb_err_int_handler()
1934 hsw_pipe_crc_irq_handler(dev, pipe); in ivb_err_int_handler()
1964 int pipe; in cpt_irq_handler() local
1993 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
1995 pipe_name(pipe), in cpt_irq_handler()
1996 I915_READ(FDI_RX_IIR(pipe))); in cpt_irq_handler()
2005 enum pipe pipe; in ilk_display_irq_handler() local
2016 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
2017 if (de_iir & DE_PIPE_VBLANK(pipe) && in ilk_display_irq_handler()
2018 intel_pipe_handle_vblank(dev, pipe)) in ilk_display_irq_handler()
2019 intel_check_page_flip(dev, pipe); in ilk_display_irq_handler()
2021 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) in ilk_display_irq_handler()
2022 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
2024 if (de_iir & DE_PIPE_CRC_DONE(pipe)) in ilk_display_irq_handler()
2025 i9xx_pipe_crc_irq_handler(dev, pipe); in ilk_display_irq_handler()
2028 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { in ilk_display_irq_handler()
2029 intel_prepare_page_flip(dev, pipe); in ilk_display_irq_handler()
2030 intel_finish_page_flip_plane(dev, pipe); in ilk_display_irq_handler()
2054 enum pipe pipe; in ivb_display_irq_handler() local
2065 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
2066 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && in ivb_display_irq_handler()
2067 intel_pipe_handle_vblank(dev, pipe)) in ivb_display_irq_handler()
2068 intel_check_page_flip(dev, pipe); in ivb_display_irq_handler()
2071 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { in ivb_display_irq_handler()
2072 intel_prepare_page_flip(dev, pipe); in ivb_display_irq_handler()
2073 intel_finish_page_flip_plane(dev, pipe); in ivb_display_irq_handler()
2174 enum pipe pipe; in gen8_irq_handler() local
2225 for_each_pipe(dev_priv, pipe) { in gen8_irq_handler()
2228 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) in gen8_irq_handler()
2231 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); in gen8_irq_handler()
2234 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); in gen8_irq_handler()
2237 intel_pipe_handle_vblank(dev, pipe)) in gen8_irq_handler()
2238 intel_check_page_flip(dev, pipe); in gen8_irq_handler()
2246 intel_prepare_page_flip(dev, pipe); in gen8_irq_handler()
2247 intel_finish_page_flip_plane(dev, pipe); in gen8_irq_handler()
2251 hsw_pipe_crc_irq_handler(dev, pipe); in gen8_irq_handler()
2255 pipe); in gen8_irq_handler()
2265 pipe_name(pipe), in gen8_irq_handler()
2409 int pipe, i; in i915_report_and_clear_eir() local
2452 for_each_pipe(dev_priv, pipe) in i915_report_and_clear_eir()
2454 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); in i915_report_and_clear_eir()
2546 static int i915_enable_vblank(struct drm_device *dev, int pipe) in i915_enable_vblank() argument
2553 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2556 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2563 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) in ironlake_enable_vblank() argument
2567 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : in ironlake_enable_vblank()
2568 DE_PIPE_VBLANK(pipe); in ironlake_enable_vblank()
2577 static int valleyview_enable_vblank(struct drm_device *dev, int pipe) in valleyview_enable_vblank() argument
2583 i915_enable_pipestat(dev_priv, pipe, in valleyview_enable_vblank()
2590 static int gen8_enable_vblank(struct drm_device *dev, int pipe) in gen8_enable_vblank() argument
2596 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; in gen8_enable_vblank()
2597 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_enable_vblank()
2598 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in gen8_enable_vblank()
2606 static void i915_disable_vblank(struct drm_device *dev, int pipe) in i915_disable_vblank() argument
2612 i915_disable_pipestat(dev_priv, pipe, in i915_disable_vblank()
2618 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) in ironlake_disable_vblank() argument
2622 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : in ironlake_disable_vblank()
2623 DE_PIPE_VBLANK(pipe); in ironlake_disable_vblank()
2630 static void valleyview_disable_vblank(struct drm_device *dev, int pipe) in valleyview_disable_vblank() argument
2636 i915_disable_pipestat(dev_priv, pipe, in valleyview_disable_vblank()
2641 static void gen8_disable_vblank(struct drm_device *dev, int pipe) in gen8_disable_vblank() argument
2647 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; in gen8_disable_vblank()
2648 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_disable_vblank()
2649 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in gen8_disable_vblank()
3045 enum pipe pipe; in vlv_display_irq_reset() local
3050 for_each_pipe(dev_priv, pipe) in vlv_display_irq_reset()
3051 I915_WRITE(PIPESTAT(pipe), 0xffff); in vlv_display_irq_reset()
3084 int pipe; in gen8_irq_reset() local
3091 for_each_pipe(dev_priv, pipe) in gen8_irq_reset()
3093 POWER_DOMAIN_PIPE(pipe))) in gen8_irq_reset()
3094 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); in gen8_irq_reset()
3280 enum pipe pipe; in valleyview_display_irqs_install() local
3285 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3286 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_install()
3293 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3294 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_install()
3314 enum pipe pipe; in valleyview_display_irqs_uninstall() local
3333 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3334 i915_disable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_uninstall()
3339 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3340 I915_WRITE(PIPESTAT(pipe), pipestat_mask); in valleyview_display_irqs_uninstall()
3443 int pipe; in gen8_de_irq_postinstall() local
3462 for_each_pipe(dev_priv, pipe) in gen8_de_irq_postinstall()
3464 POWER_DOMAIN_PIPE(pipe))) in gen8_de_irq_postinstall()
3465 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, in gen8_de_irq_postinstall()
3466 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3573 int pipe; in i8xx_irq_preinstall() local
3575 for_each_pipe(dev_priv, pipe) in i8xx_irq_preinstall()
3576 I915_WRITE(PIPESTAT(pipe), 0); in i8xx_irq_preinstall()
3617 int plane, int pipe, u32 iir) in i8xx_handle_vblank() argument
3622 if (!intel_pipe_handle_vblank(dev, pipe)) in i8xx_handle_vblank()
3638 intel_finish_page_flip(dev, pipe); in i8xx_handle_vblank()
3642 intel_check_page_flip(dev, pipe); in i8xx_handle_vblank()
3652 int pipe; in i8xx_irq_handler() local
3674 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3675 int reg = PIPESTAT(pipe); in i8xx_irq_handler()
3676 pipe_stats[pipe] = I915_READ(reg); in i8xx_irq_handler()
3681 if (pipe_stats[pipe] & 0x8000ffff) in i8xx_irq_handler()
3682 I915_WRITE(reg, pipe_stats[pipe]); in i8xx_irq_handler()
3692 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3693 int plane = pipe; in i8xx_irq_handler()
3697 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i8xx_irq_handler()
3698 i8xx_handle_vblank(dev, plane, pipe, iir)) in i8xx_irq_handler()
3701 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i8xx_irq_handler()
3702 i9xx_pipe_crc_irq_handler(dev, pipe); in i8xx_irq_handler()
3704 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i8xx_irq_handler()
3706 pipe); in i8xx_irq_handler()
3718 int pipe; in i8xx_irq_uninstall() local
3720 for_each_pipe(dev_priv, pipe) { in i8xx_irq_uninstall()
3722 I915_WRITE(PIPESTAT(pipe), 0); in i8xx_irq_uninstall()
3723 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); in i8xx_irq_uninstall()
3733 int pipe; in i915_irq_preinstall() local
3741 for_each_pipe(dev_priv, pipe) in i915_irq_preinstall()
3742 I915_WRITE(PIPESTAT(pipe), 0); in i915_irq_preinstall()
3799 int plane, int pipe, u32 iir) in i915_handle_vblank() argument
3804 if (!intel_pipe_handle_vblank(dev, pipe)) in i915_handle_vblank()
3820 intel_finish_page_flip(dev, pipe); in i915_handle_vblank()
3824 intel_check_page_flip(dev, pipe); in i915_handle_vblank()
3836 int pipe, ret = IRQ_NONE; in i915_irq_handler() local
3855 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
3856 int reg = PIPESTAT(pipe); in i915_irq_handler()
3857 pipe_stats[pipe] = I915_READ(reg); in i915_irq_handler()
3860 if (pipe_stats[pipe] & 0x8000ffff) { in i915_irq_handler()
3861 I915_WRITE(reg, pipe_stats[pipe]); in i915_irq_handler()
3881 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
3882 int plane = pipe; in i915_irq_handler()
3886 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i915_irq_handler()
3887 i915_handle_vblank(dev, plane, pipe, iir)) in i915_irq_handler()
3890 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i915_irq_handler()
3893 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i915_irq_handler()
3894 i9xx_pipe_crc_irq_handler(dev, pipe); in i915_irq_handler()
3896 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_irq_handler()
3898 pipe); in i915_irq_handler()
3929 int pipe; in i915_irq_uninstall() local
3937 for_each_pipe(dev_priv, pipe) { in i915_irq_uninstall()
3939 I915_WRITE(PIPESTAT(pipe), 0); in i915_irq_uninstall()
3940 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); in i915_irq_uninstall()
3951 int pipe; in i965_irq_preinstall() local
3957 for_each_pipe(dev_priv, pipe) in i965_irq_preinstall()
3958 I915_WRITE(PIPESTAT(pipe), 0); in i965_irq_preinstall()
4056 int ret = IRQ_NONE, pipe; in i965_irq_handler() local
4079 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4080 int reg = PIPESTAT(pipe); in i965_irq_handler()
4081 pipe_stats[pipe] = I915_READ(reg); in i965_irq_handler()
4086 if (pipe_stats[pipe] & 0x8000ffff) { in i965_irq_handler()
4087 I915_WRITE(reg, pipe_stats[pipe]); in i965_irq_handler()
4110 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4111 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && in i965_irq_handler()
4112 i915_handle_vblank(dev, pipe, pipe, iir)) in i965_irq_handler()
4113 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); in i965_irq_handler()
4115 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i965_irq_handler()
4118 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i965_irq_handler()
4119 i9xx_pipe_crc_irq_handler(dev, pipe); in i965_irq_handler()
4121 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_irq_handler()
4122 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_irq_handler()
4155 int pipe; in i965_irq_uninstall() local
4164 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4165 I915_WRITE(PIPESTAT(pipe), 0); in i965_irq_uninstall()
4169 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4170 I915_WRITE(PIPESTAT(pipe), in i965_irq_uninstall()
4171 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); in i965_irq_uninstall()