Lines Matching refs:dev_priv
141 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
145 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) in ironlake_enable_display_irq() argument
147 assert_spin_locked(&dev_priv->irq_lock); in ironlake_enable_display_irq()
149 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ironlake_enable_display_irq()
152 if ((dev_priv->irq_mask & mask) != 0) { in ironlake_enable_display_irq()
153 dev_priv->irq_mask &= ~mask; in ironlake_enable_display_irq()
154 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_enable_display_irq()
160 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) in ironlake_disable_display_irq() argument
162 assert_spin_locked(&dev_priv->irq_lock); in ironlake_disable_display_irq()
164 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ironlake_disable_display_irq()
167 if ((dev_priv->irq_mask & mask) != mask) { in ironlake_disable_display_irq()
168 dev_priv->irq_mask |= mask; in ironlake_disable_display_irq()
169 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_disable_display_irq()
180 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, in ilk_update_gt_irq() argument
184 assert_spin_locked(&dev_priv->irq_lock); in ilk_update_gt_irq()
188 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ilk_update_gt_irq()
191 dev_priv->gt_irq_mask &= ~interrupt_mask; in ilk_update_gt_irq()
192 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); in ilk_update_gt_irq()
193 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); in ilk_update_gt_irq()
197 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen5_enable_gt_irq() argument
199 ilk_update_gt_irq(dev_priv, mask, mask); in gen5_enable_gt_irq()
202 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen5_disable_gt_irq() argument
204 ilk_update_gt_irq(dev_priv, mask, 0); in gen5_disable_gt_irq()
207 static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) in gen6_pm_iir() argument
209 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; in gen6_pm_iir()
212 static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) in gen6_pm_imr() argument
214 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; in gen6_pm_imr()
217 static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) in gen6_pm_ier() argument
219 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; in gen6_pm_ier()
228 static void snb_update_pm_irq(struct drm_i915_private *dev_priv, in snb_update_pm_irq() argument
236 assert_spin_locked(&dev_priv->irq_lock); in snb_update_pm_irq()
238 new_val = dev_priv->pm_irq_mask; in snb_update_pm_irq()
242 if (new_val != dev_priv->pm_irq_mask) { in snb_update_pm_irq()
243 dev_priv->pm_irq_mask = new_val; in snb_update_pm_irq()
244 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); in snb_update_pm_irq()
245 POSTING_READ(gen6_pm_imr(dev_priv)); in snb_update_pm_irq()
249 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen6_enable_pm_irq() argument
251 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in gen6_enable_pm_irq()
254 snb_update_pm_irq(dev_priv, mask, mask); in gen6_enable_pm_irq()
257 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, in __gen6_disable_pm_irq() argument
260 snb_update_pm_irq(dev_priv, mask, 0); in __gen6_disable_pm_irq()
263 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) in gen6_disable_pm_irq() argument
265 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in gen6_disable_pm_irq()
268 __gen6_disable_pm_irq(dev_priv, mask); in gen6_disable_pm_irq()
273 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_reset_rps_interrupts() local
274 uint32_t reg = gen6_pm_iir(dev_priv); in gen6_reset_rps_interrupts()
276 spin_lock_irq(&dev_priv->irq_lock); in gen6_reset_rps_interrupts()
277 I915_WRITE(reg, dev_priv->pm_rps_events); in gen6_reset_rps_interrupts()
278 I915_WRITE(reg, dev_priv->pm_rps_events); in gen6_reset_rps_interrupts()
280 dev_priv->rps.pm_iir = 0; in gen6_reset_rps_interrupts()
281 spin_unlock_irq(&dev_priv->irq_lock); in gen6_reset_rps_interrupts()
286 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_enable_rps_interrupts() local
288 spin_lock_irq(&dev_priv->irq_lock); in gen6_enable_rps_interrupts()
290 WARN_ON(dev_priv->rps.pm_iir); in gen6_enable_rps_interrupts()
291 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
292 dev_priv->rps.interrupts_enabled = true; in gen6_enable_rps_interrupts()
293 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | in gen6_enable_rps_interrupts()
294 dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
295 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
297 spin_unlock_irq(&dev_priv->irq_lock); in gen6_enable_rps_interrupts()
300 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) in gen6_sanitize_rps_pm_mask() argument
308 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) in gen6_sanitize_rps_pm_mask()
311 if (INTEL_INFO(dev_priv)->gen >= 8) in gen6_sanitize_rps_pm_mask()
319 struct drm_i915_private *dev_priv = dev->dev_private; in gen6_disable_rps_interrupts() local
321 spin_lock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
322 dev_priv->rps.interrupts_enabled = false; in gen6_disable_rps_interrupts()
323 spin_unlock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
325 cancel_work_sync(&dev_priv->rps.work); in gen6_disable_rps_interrupts()
327 spin_lock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
329 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); in gen6_disable_rps_interrupts()
331 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_disable_rps_interrupts()
332 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & in gen6_disable_rps_interrupts()
333 ~dev_priv->pm_rps_events); in gen6_disable_rps_interrupts()
335 spin_unlock_irq(&dev_priv->irq_lock); in gen6_disable_rps_interrupts()
346 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, in ibx_display_interrupt_update() argument
356 assert_spin_locked(&dev_priv->irq_lock); in ibx_display_interrupt_update()
358 if (WARN_ON(!intel_irqs_enabled(dev_priv))) in ibx_display_interrupt_update()
366 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_enable_pipestat() argument
372 assert_spin_locked(&dev_priv->irq_lock); in __i915_enable_pipestat()
373 WARN_ON(!intel_irqs_enabled(dev_priv)); in __i915_enable_pipestat()
384 dev_priv->pipestat_irq_mask[pipe] |= status_mask; in __i915_enable_pipestat()
393 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in __i915_disable_pipestat() argument
399 assert_spin_locked(&dev_priv->irq_lock); in __i915_disable_pipestat()
400 WARN_ON(!intel_irqs_enabled(dev_priv)); in __i915_disable_pipestat()
411 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; in __i915_disable_pipestat()
447 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_enable_pipestat() argument
452 if (IS_VALLEYVIEW(dev_priv->dev)) in i915_enable_pipestat()
453 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, in i915_enable_pipestat()
457 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_enable_pipestat()
461 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, in i915_disable_pipestat() argument
466 if (IS_VALLEYVIEW(dev_priv->dev)) in i915_disable_pipestat()
467 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, in i915_disable_pipestat()
471 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); in i915_disable_pipestat()
479 struct drm_i915_private *dev_priv = dev->dev_private; in i915_enable_asle_pipestat() local
481 if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) in i915_enable_asle_pipestat()
484 spin_lock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
486 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
488 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
491 spin_unlock_irq(&dev_priv->irq_lock); in i915_enable_asle_pipestat()
555 struct drm_i915_private *dev_priv = dev->dev_private; in i915_get_vblank_counter() local
560 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); in i915_get_vblank_counter()
604 struct drm_i915_private *dev_priv = dev->dev_private; in gm45_get_vblank_counter() local
616 struct drm_i915_private *dev_priv = dev->dev_private; in __intel_get_crtc_scanline() local
626 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()
628 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
641 struct drm_i915_private *dev_priv = dev->dev_private; in i915_get_crtc_scanoutpos() local
642 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in i915_get_crtc_scanoutpos()
676 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
694 …position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHI… in i915_get_crtc_scanoutpos()
731 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in i915_get_crtc_scanoutpos()
763 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; in intel_get_crtc_scanline() local
767 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
769 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); in intel_get_crtc_scanline()
828 struct drm_i915_private *dev_priv = in i915_digport_work_func() local
835 spin_lock_irq(&dev_priv->irq_lock); in i915_digport_work_func()
836 long_port_mask = dev_priv->long_hpd_port_mask; in i915_digport_work_func()
837 dev_priv->long_hpd_port_mask = 0; in i915_digport_work_func()
838 short_port_mask = dev_priv->short_hpd_port_mask; in i915_digport_work_func()
839 dev_priv->short_hpd_port_mask = 0; in i915_digport_work_func()
840 spin_unlock_irq(&dev_priv->irq_lock); in i915_digport_work_func()
845 intel_dig_port = dev_priv->hpd_irq_port[i]; in i915_digport_work_func()
867 spin_lock_irq(&dev_priv->irq_lock); in i915_digport_work_func()
868 dev_priv->hpd_event_bits |= old_bits; in i915_digport_work_func()
869 spin_unlock_irq(&dev_priv->irq_lock); in i915_digport_work_func()
870 schedule_work(&dev_priv->hotplug_work); in i915_digport_work_func()
881 struct drm_i915_private *dev_priv = in i915_hotplug_work_func() local
883 struct drm_device *dev = dev_priv->dev; in i915_hotplug_work_func()
895 spin_lock_irq(&dev_priv->irq_lock); in i915_hotplug_work_func()
897 hpd_event_bits = dev_priv->hpd_event_bits; in i915_hotplug_work_func()
898 dev_priv->hpd_event_bits = 0; in i915_hotplug_work_func()
905 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && in i915_hotplug_work_func()
910 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; in i915_hotplug_work_func()
925 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work, in i915_hotplug_work_func()
929 spin_unlock_irq(&dev_priv->irq_lock); in i915_hotplug_work_func()
951 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_rps_change_irq_handler() local
959 new_delay = dev_priv->ips.cur_delay; in ironlake_rps_change_irq_handler()
969 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) in ironlake_rps_change_irq_handler()
970 new_delay = dev_priv->ips.cur_delay - 1; in ironlake_rps_change_irq_handler()
971 if (new_delay < dev_priv->ips.max_delay) in ironlake_rps_change_irq_handler()
972 new_delay = dev_priv->ips.max_delay; in ironlake_rps_change_irq_handler()
974 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) in ironlake_rps_change_irq_handler()
975 new_delay = dev_priv->ips.cur_delay + 1; in ironlake_rps_change_irq_handler()
976 if (new_delay > dev_priv->ips.min_delay) in ironlake_rps_change_irq_handler()
977 new_delay = dev_priv->ips.min_delay; in ironlake_rps_change_irq_handler()
981 dev_priv->ips.cur_delay = new_delay; in ironlake_rps_change_irq_handler()
999 static void vlv_c0_read(struct drm_i915_private *dev_priv, in vlv_c0_read() argument
1002 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); in vlv_c0_read()
1007 static bool vlv_c0_above(struct drm_i915_private *dev_priv, in vlv_c0_above() argument
1018 time *= threshold * dev_priv->mem_freq; in vlv_c0_above()
1031 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) in gen6_rps_reset_ei() argument
1033 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); in gen6_rps_reset_ei()
1034 dev_priv->rps.up_ei = dev_priv->rps.down_ei; in gen6_rps_reset_ei()
1037 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) in vlv_wa_c0_ei() argument
1045 vlv_c0_read(dev_priv, &now); in vlv_wa_c0_ei()
1050 if (!vlv_c0_above(dev_priv, in vlv_wa_c0_ei()
1051 &dev_priv->rps.down_ei, &now, in vlv_wa_c0_ei()
1054 dev_priv->rps.down_ei = now; in vlv_wa_c0_ei()
1058 if (vlv_c0_above(dev_priv, in vlv_wa_c0_ei()
1059 &dev_priv->rps.up_ei, &now, in vlv_wa_c0_ei()
1062 dev_priv->rps.up_ei = now; in vlv_wa_c0_ei()
1070 struct drm_i915_private *dev_priv = in gen6_pm_rps_work() local
1075 spin_lock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1077 if (!dev_priv->rps.interrupts_enabled) { in gen6_pm_rps_work()
1078 spin_unlock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1081 pm_iir = dev_priv->rps.pm_iir; in gen6_pm_rps_work()
1082 dev_priv->rps.pm_iir = 0; in gen6_pm_rps_work()
1084 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); in gen6_pm_rps_work()
1085 spin_unlock_irq(&dev_priv->irq_lock); in gen6_pm_rps_work()
1088 WARN_ON(pm_iir & ~dev_priv->pm_rps_events); in gen6_pm_rps_work()
1090 if ((pm_iir & dev_priv->pm_rps_events) == 0) in gen6_pm_rps_work()
1093 mutex_lock(&dev_priv->rps.hw_lock); in gen6_pm_rps_work()
1095 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); in gen6_pm_rps_work()
1097 adj = dev_priv->rps.last_adj; in gen6_pm_rps_work()
1103 adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1; in gen6_pm_rps_work()
1105 new_delay = dev_priv->rps.cur_freq + adj; in gen6_pm_rps_work()
1111 if (new_delay < dev_priv->rps.efficient_freq) in gen6_pm_rps_work()
1112 new_delay = dev_priv->rps.efficient_freq; in gen6_pm_rps_work()
1114 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) in gen6_pm_rps_work()
1115 new_delay = dev_priv->rps.efficient_freq; in gen6_pm_rps_work()
1117 new_delay = dev_priv->rps.min_freq_softlimit; in gen6_pm_rps_work()
1124 adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1; in gen6_pm_rps_work()
1126 new_delay = dev_priv->rps.cur_freq + adj; in gen6_pm_rps_work()
1128 new_delay = dev_priv->rps.cur_freq; in gen6_pm_rps_work()
1135 dev_priv->rps.min_freq_softlimit, in gen6_pm_rps_work()
1136 dev_priv->rps.max_freq_softlimit); in gen6_pm_rps_work()
1138 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; in gen6_pm_rps_work()
1140 intel_set_rps(dev_priv->dev, new_delay); in gen6_pm_rps_work()
1142 mutex_unlock(&dev_priv->rps.hw_lock); in gen6_pm_rps_work()
1157 struct drm_i915_private *dev_priv = in ivybridge_parity_work() local
1168 mutex_lock(&dev_priv->dev->struct_mutex); in ivybridge_parity_work()
1171 if (WARN_ON(!dev_priv->l3_parity.which_slice)) in ivybridge_parity_work()
1178 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { in ivybridge_parity_work()
1182 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) in ivybridge_parity_work()
1185 dev_priv->l3_parity.which_slice &= ~(1<<slice); in ivybridge_parity_work()
1204 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, in ivybridge_parity_work()
1219 WARN_ON(dev_priv->l3_parity.which_slice); in ivybridge_parity_work()
1220 spin_lock_irq(&dev_priv->irq_lock); in ivybridge_parity_work()
1221 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); in ivybridge_parity_work()
1222 spin_unlock_irq(&dev_priv->irq_lock); in ivybridge_parity_work()
1224 mutex_unlock(&dev_priv->dev->struct_mutex); in ivybridge_parity_work()
1229 struct drm_i915_private *dev_priv = dev->dev_private; in ivybridge_parity_error_irq_handler() local
1234 spin_lock(&dev_priv->irq_lock); in ivybridge_parity_error_irq_handler()
1235 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); in ivybridge_parity_error_irq_handler()
1236 spin_unlock(&dev_priv->irq_lock); in ivybridge_parity_error_irq_handler()
1240 dev_priv->l3_parity.which_slice |= 1 << 1; in ivybridge_parity_error_irq_handler()
1243 dev_priv->l3_parity.which_slice |= 1 << 0; in ivybridge_parity_error_irq_handler()
1245 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); in ivybridge_parity_error_irq_handler()
1249 struct drm_i915_private *dev_priv, in ilk_gt_irq_handler() argument
1254 notify_ring(dev, &dev_priv->ring[RCS]); in ilk_gt_irq_handler()
1256 notify_ring(dev, &dev_priv->ring[VCS]); in ilk_gt_irq_handler()
1260 struct drm_i915_private *dev_priv, in snb_gt_irq_handler() argument
1266 notify_ring(dev, &dev_priv->ring[RCS]); in snb_gt_irq_handler()
1268 notify_ring(dev, &dev_priv->ring[VCS]); in snb_gt_irq_handler()
1270 notify_ring(dev, &dev_priv->ring[BCS]); in snb_gt_irq_handler()
1282 struct drm_i915_private *dev_priv, in gen8_gt_irq_handler() argument
1297 ring = &dev_priv->ring[RCS]; in gen8_gt_irq_handler()
1304 ring = &dev_priv->ring[BCS]; in gen8_gt_irq_handler()
1320 ring = &dev_priv->ring[VCS]; in gen8_gt_irq_handler()
1327 ring = &dev_priv->ring[VCS2]; in gen8_gt_irq_handler()
1338 if (tmp & dev_priv->pm_rps_events) { in gen8_gt_irq_handler()
1340 tmp & dev_priv->pm_rps_events); in gen8_gt_irq_handler()
1342 gen6_rps_irq_handler(dev_priv, tmp); in gen8_gt_irq_handler()
1354 ring = &dev_priv->ring[VECS]; in gen8_gt_irq_handler()
1420 struct drm_i915_private *dev_priv = dev->dev_private; in intel_hpd_irq_handler() local
1434 spin_lock(&dev_priv->irq_lock); in intel_hpd_irq_handler()
1440 if (port && dev_priv->hpd_irq_port[port]) { in intel_hpd_irq_handler()
1457 dev_priv->long_hpd_port_mask |= (1 << port); in intel_hpd_irq_handler()
1461 dev_priv->short_hpd_port_mask |= (1 << port); in intel_hpd_irq_handler()
1470 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { in intel_hpd_irq_handler()
1485 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) in intel_hpd_irq_handler()
1489 dev_priv->hpd_event_bits |= (1 << i); in intel_hpd_irq_handler()
1493 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, in intel_hpd_irq_handler()
1494 dev_priv->hpd_stats[i].hpd_last_jiffies in intel_hpd_irq_handler()
1496 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; in intel_hpd_irq_handler()
1497 dev_priv->hpd_stats[i].hpd_cnt = 0; in intel_hpd_irq_handler()
1499 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { in intel_hpd_irq_handler()
1500 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; in intel_hpd_irq_handler()
1501 dev_priv->hpd_event_bits &= ~(1 << i); in intel_hpd_irq_handler()
1505 dev_priv->hpd_stats[i].hpd_cnt++; in intel_hpd_irq_handler()
1507 dev_priv->hpd_stats[i].hpd_cnt); in intel_hpd_irq_handler()
1512 dev_priv->display.hpd_irq_setup(dev); in intel_hpd_irq_handler()
1513 spin_unlock(&dev_priv->irq_lock); in intel_hpd_irq_handler()
1522 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work); in intel_hpd_irq_handler()
1524 schedule_work(&dev_priv->hotplug_work); in intel_hpd_irq_handler()
1529 struct drm_i915_private *dev_priv = dev->dev_private; in gmbus_irq_handler() local
1531 wake_up_all(&dev_priv->gmbus_wait_queue); in gmbus_irq_handler()
1536 struct drm_i915_private *dev_priv = dev->dev_private; in dp_aux_irq_handler() local
1538 wake_up_all(&dev_priv->gmbus_wait_queue); in dp_aux_irq_handler()
1547 struct drm_i915_private *dev_priv = dev->dev_private; in display_pipe_crc_irq_handler() local
1548 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; in display_pipe_crc_irq_handler()
1596 struct drm_i915_private *dev_priv = dev->dev_private; in hsw_pipe_crc_irq_handler() local
1605 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_pipe_crc_irq_handler() local
1617 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_pipe_crc_irq_handler() local
1640 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) in gen6_rps_irq_handler() argument
1642 if (pm_iir & dev_priv->pm_rps_events) { in gen6_rps_irq_handler()
1643 spin_lock(&dev_priv->irq_lock); in gen6_rps_irq_handler()
1644 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); in gen6_rps_irq_handler()
1645 if (dev_priv->rps.interrupts_enabled) { in gen6_rps_irq_handler()
1646 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; in gen6_rps_irq_handler()
1647 queue_work(dev_priv->wq, &dev_priv->rps.work); in gen6_rps_irq_handler()
1649 spin_unlock(&dev_priv->irq_lock); in gen6_rps_irq_handler()
1652 if (INTEL_INFO(dev_priv)->gen >= 8) in gen6_rps_irq_handler()
1655 if (HAS_VEBOX(dev_priv->dev)) { in gen6_rps_irq_handler()
1657 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); in gen6_rps_irq_handler()
1674 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_pipestat_irq_handler() local
1678 spin_lock(&dev_priv->irq_lock); in valleyview_pipestat_irq_handler()
1679 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1706 mask |= dev_priv->pipestat_irq_mask[pipe]; in valleyview_pipestat_irq_handler()
1722 spin_unlock(&dev_priv->irq_lock); in valleyview_pipestat_irq_handler()
1724 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
1738 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
1747 struct drm_i915_private *dev_priv = dev->dev_private; in i9xx_hpd_irq_handler() local
1777 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_handler() local
1781 if (!intel_irqs_enabled(dev_priv)) in valleyview_irq_handler()
1809 snb_gt_irq_handler(dev, dev_priv, gt_iir); in valleyview_irq_handler()
1811 gen6_rps_irq_handler(dev_priv, pm_iir); in valleyview_irq_handler()
1824 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_handler() local
1828 if (!intel_irqs_enabled(dev_priv)) in cherryview_irq_handler()
1851 gen8_gt_irq_handler(dev, dev_priv, master_ctl); in cherryview_irq_handler()
1866 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_handler() local
1899 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
1911 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); in ibx_irq_handler()
1914 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); in ibx_irq_handler()
1919 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_err_int_handler() local
1926 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
1928 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
1943 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_serr_int_handler() local
1950 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); in cpt_serr_int_handler()
1953 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); in cpt_serr_int_handler()
1956 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); in cpt_serr_int_handler()
1963 struct drm_i915_private *dev_priv = dev->dev_private; in cpt_irq_handler() local
1993 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
2004 struct drm_i915_private *dev_priv = dev->dev_private; in ilk_display_irq_handler() local
2016 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
2022 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
2053 struct drm_i915_private *dev_priv = dev->dev_private; in ivb_display_irq_handler() local
2065 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
2099 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_handler() local
2103 if (!intel_irqs_enabled(dev_priv)) in ironlake_irq_handler()
2133 snb_gt_irq_handler(dev, dev_priv, gt_iir); in ironlake_irq_handler()
2135 ilk_gt_irq_handler(dev, dev_priv, gt_iir); in ironlake_irq_handler()
2153 gen6_rps_irq_handler(dev_priv, pm_iir); in ironlake_irq_handler()
2170 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_handler() local
2177 if (!intel_irqs_enabled(dev_priv)) in gen8_irq_handler()
2194 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl); in gen8_irq_handler()
2225 for_each_pipe(dev_priv, pipe) { in gen8_irq_handler()
2254 intel_cpu_fifo_underrun_irq_handler(dev_priv, in gen8_irq_handler()
2293 static void i915_error_wake_up(struct drm_i915_private *dev_priv, in i915_error_wake_up() argument
2307 for_each_ring(ring, dev_priv, i) in i915_error_wake_up()
2311 wake_up_all(&dev_priv->pending_flip_queue); in i915_error_wake_up()
2318 wake_up_all(&dev_priv->gpu_error.reset_queue); in i915_error_wake_up()
2329 struct drm_i915_private *dev_priv = to_i915(dev); in i915_reset_and_wakeup() local
2330 struct i915_gpu_error *error = &dev_priv->gpu_error; in i915_reset_and_wakeup()
2360 intel_runtime_pm_get(dev_priv); in i915_reset_and_wakeup()
2374 intel_runtime_pm_put(dev_priv); in i915_reset_and_wakeup()
2388 atomic_inc(&dev_priv->gpu_error.reset_counter); in i915_reset_and_wakeup()
2400 i915_error_wake_up(dev_priv, true); in i915_reset_and_wakeup()
2406 struct drm_i915_private *dev_priv = dev->dev_private; in i915_report_and_clear_eir() local
2452 for_each_pipe(dev_priv, pipe) in i915_report_and_clear_eir()
2509 struct drm_i915_private *dev_priv = dev->dev_private; in i915_handle_error() local
2522 &dev_priv->gpu_error.reset_counter); in i915_handle_error()
2537 i915_error_wake_up(dev_priv, false); in i915_handle_error()
2548 struct drm_i915_private *dev_priv = dev->dev_private; in i915_enable_vblank() local
2551 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i915_enable_vblank()
2553 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2556 i915_enable_pipestat(dev_priv, pipe, in i915_enable_vblank()
2558 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i915_enable_vblank()
2565 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_enable_vblank() local
2570 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ironlake_enable_vblank()
2571 ironlake_enable_display_irq(dev_priv, bit); in ironlake_enable_vblank()
2572 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ironlake_enable_vblank()
2579 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_enable_vblank() local
2582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in valleyview_enable_vblank()
2583 i915_enable_pipestat(dev_priv, pipe, in valleyview_enable_vblank()
2585 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in valleyview_enable_vblank()
2592 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_enable_vblank() local
2595 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in gen8_enable_vblank()
2596 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; in gen8_enable_vblank()
2597 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_enable_vblank()
2599 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in gen8_enable_vblank()
2608 struct drm_i915_private *dev_priv = dev->dev_private; in i915_disable_vblank() local
2611 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in i915_disable_vblank()
2612 i915_disable_pipestat(dev_priv, pipe, in i915_disable_vblank()
2615 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in i915_disable_vblank()
2620 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_disable_vblank() local
2625 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in ironlake_disable_vblank()
2626 ironlake_disable_display_irq(dev_priv, bit); in ironlake_disable_vblank()
2627 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in ironlake_disable_vblank()
2632 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_disable_vblank() local
2635 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in valleyview_disable_vblank()
2636 i915_disable_pipestat(dev_priv, pipe, in valleyview_disable_vblank()
2638 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in valleyview_disable_vblank()
2643 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_disable_vblank() local
2646 spin_lock_irqsave(&dev_priv->irq_lock, irqflags); in gen8_disable_vblank()
2647 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; in gen8_disable_vblank()
2648 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in gen8_disable_vblank()
2650 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); in gen8_disable_vblank()
2675 struct drm_i915_private *dev_priv = ring->dev->dev_private; in semaphore_wait_to_signaller_ring() local
2679 if (INTEL_INFO(dev_priv->dev)->gen >= 8) { in semaphore_wait_to_signaller_ring()
2680 for_each_ring(signaller, dev_priv, i) { in semaphore_wait_to_signaller_ring()
2690 for_each_ring(signaller, dev_priv, i) { in semaphore_wait_to_signaller_ring()
2708 struct drm_i915_private *dev_priv = ring->dev->dev_private; in semaphore_waits_for() local
2758 struct drm_i915_private *dev_priv = ring->dev->dev_private; in semaphore_passed() local
2783 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) in semaphore_clear_deadlocks() argument
2788 for_each_ring(ring, dev_priv, i) in semaphore_clear_deadlocks()
2796 struct drm_i915_private *dev_priv = dev->dev_private; in ring_stuck() local
2853 struct drm_i915_private *dev_priv = in i915_hangcheck_elapsed() local
2854 container_of(work, typeof(*dev_priv), in i915_hangcheck_elapsed()
2856 struct drm_device *dev = dev_priv->dev; in i915_hangcheck_elapsed()
2868 for_each_ring(ring, dev_priv, i) { in i915_hangcheck_elapsed()
2873 semaphore_clear_deadlocks(dev_priv); in i915_hangcheck_elapsed()
2884 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { in i915_hangcheck_elapsed()
2885 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) in i915_hangcheck_elapsed()
2950 for_each_ring(ring, dev_priv, i) { in i915_hangcheck_elapsed()
2986 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_reset() local
3007 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_pre_postinstall() local
3019 struct drm_i915_private *dev_priv = dev->dev_private; in gen5_gt_irq_reset() local
3030 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_reset() local
3043 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) in vlv_display_irq_reset() argument
3050 for_each_pipe(dev_priv, pipe) in vlv_display_irq_reset()
3058 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_preinstall() local
3070 vlv_display_irq_reset(dev_priv); in valleyview_irq_preinstall()
3073 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) in gen8_gt_irq_reset() argument
3083 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_reset() local
3089 gen8_gt_irq_reset(dev_priv); in gen8_irq_reset()
3091 for_each_pipe(dev_priv, pipe) in gen8_irq_reset()
3092 if (intel_display_power_is_enabled(dev_priv, in gen8_irq_reset()
3103 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, in gen8_irq_power_well_post_enable() argument
3108 spin_lock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3111 dev_priv->de_irq_mask[PIPE_A], in gen8_irq_power_well_post_enable()
3112 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); in gen8_irq_power_well_post_enable()
3115 dev_priv->de_irq_mask[PIPE_B], in gen8_irq_power_well_post_enable()
3116 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); in gen8_irq_power_well_post_enable()
3119 dev_priv->de_irq_mask[PIPE_C], in gen8_irq_power_well_post_enable()
3120 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); in gen8_irq_power_well_post_enable()
3121 spin_unlock_irq(&dev_priv->irq_lock); in gen8_irq_power_well_post_enable()
3126 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_preinstall() local
3131 gen8_gt_irq_reset(dev_priv); in cherryview_irq_preinstall()
3137 vlv_display_irq_reset(dev_priv); in cherryview_irq_preinstall()
3142 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_hpd_irq_setup() local
3149 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) in ibx_hpd_irq_setup()
3154 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) in ibx_hpd_irq_setup()
3158 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); in ibx_hpd_irq_setup()
3176 struct drm_i915_private *dev_priv = dev->dev_private; in ibx_irq_postinstall() local
3193 struct drm_i915_private *dev_priv = dev->dev_private; in gen5_gt_irq_postinstall() local
3198 dev_priv->gt_irq_mask = ~0; in gen5_gt_irq_postinstall()
3201 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); in gen5_gt_irq_postinstall()
3213 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); in gen5_gt_irq_postinstall()
3223 dev_priv->pm_irq_mask = 0xffffffff; in gen5_gt_irq_postinstall()
3224 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); in gen5_gt_irq_postinstall()
3230 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_postinstall() local
3250 dev_priv->irq_mask = ~display_mask; in ironlake_irq_postinstall()
3256 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); in ironlake_irq_postinstall()
3268 spin_lock_irq(&dev_priv->irq_lock); in ironlake_irq_postinstall()
3269 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); in ironlake_irq_postinstall()
3270 spin_unlock_irq(&dev_priv->irq_lock); in ironlake_irq_postinstall()
3276 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) in valleyview_display_irqs_install() argument
3285 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3292 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_install()
3293 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_install()
3294 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_install()
3299 if (IS_CHERRYVIEW(dev_priv)) in valleyview_display_irqs_install()
3301 dev_priv->irq_mask &= ~iir_mask; in valleyview_display_irqs_install()
3305 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); in valleyview_display_irqs_install()
3306 I915_WRITE(VLV_IMR, dev_priv->irq_mask); in valleyview_display_irqs_install()
3310 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) in valleyview_display_irqs_uninstall() argument
3319 if (IS_CHERRYVIEW(dev_priv)) in valleyview_display_irqs_uninstall()
3322 dev_priv->irq_mask |= iir_mask; in valleyview_display_irqs_uninstall()
3323 I915_WRITE(VLV_IMR, dev_priv->irq_mask); in valleyview_display_irqs_uninstall()
3324 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); in valleyview_display_irqs_uninstall()
3332 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_uninstall()
3333 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3334 i915_disable_pipestat(dev_priv, pipe, pipestat_mask); in valleyview_display_irqs_uninstall()
3339 for_each_pipe(dev_priv, pipe) in valleyview_display_irqs_uninstall()
3344 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_enable_display_irqs() argument
3346 assert_spin_locked(&dev_priv->irq_lock); in valleyview_enable_display_irqs()
3348 if (dev_priv->display_irqs_enabled) in valleyview_enable_display_irqs()
3351 dev_priv->display_irqs_enabled = true; in valleyview_enable_display_irqs()
3353 if (intel_irqs_enabled(dev_priv)) in valleyview_enable_display_irqs()
3354 valleyview_display_irqs_install(dev_priv); in valleyview_enable_display_irqs()
3357 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) in valleyview_disable_display_irqs() argument
3359 assert_spin_locked(&dev_priv->irq_lock); in valleyview_disable_display_irqs()
3361 if (!dev_priv->display_irqs_enabled) in valleyview_disable_display_irqs()
3364 dev_priv->display_irqs_enabled = false; in valleyview_disable_display_irqs()
3366 if (intel_irqs_enabled(dev_priv)) in valleyview_disable_display_irqs()
3367 valleyview_display_irqs_uninstall(dev_priv); in valleyview_disable_display_irqs()
3370 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) in vlv_display_irq_postinstall() argument
3372 dev_priv->irq_mask = ~0; in vlv_display_irq_postinstall()
3379 I915_WRITE(VLV_IER, ~dev_priv->irq_mask); in vlv_display_irq_postinstall()
3380 I915_WRITE(VLV_IMR, dev_priv->irq_mask); in vlv_display_irq_postinstall()
3385 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_irq_postinstall()
3386 if (dev_priv->display_irqs_enabled) in vlv_display_irq_postinstall()
3387 valleyview_display_irqs_install(dev_priv); in vlv_display_irq_postinstall()
3388 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_irq_postinstall()
3393 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_postinstall() local
3395 vlv_display_irq_postinstall(dev_priv); in valleyview_irq_postinstall()
3410 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_gt_irq_postinstall() argument
3428 dev_priv->pm_irq_mask = 0xffffffff; in gen8_gt_irq_postinstall()
3435 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); in gen8_gt_irq_postinstall()
3439 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) in gen8_de_irq_postinstall() argument
3446 if (IS_GEN9(dev_priv)) { in gen8_de_irq_postinstall()
3458 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3459 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3460 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; in gen8_de_irq_postinstall()
3462 for_each_pipe(dev_priv, pipe) in gen8_de_irq_postinstall()
3463 if (intel_display_power_is_enabled(dev_priv, in gen8_de_irq_postinstall()
3466 dev_priv->de_irq_mask[pipe], in gen8_de_irq_postinstall()
3474 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_postinstall() local
3478 gen8_gt_irq_postinstall(dev_priv); in gen8_irq_postinstall()
3479 gen8_de_irq_postinstall(dev_priv); in gen8_irq_postinstall()
3491 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_postinstall() local
3493 vlv_display_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
3495 gen8_gt_irq_postinstall(dev_priv); in cherryview_irq_postinstall()
3505 struct drm_i915_private *dev_priv = dev->dev_private; in gen8_irq_uninstall() local
3507 if (!dev_priv) in gen8_irq_uninstall()
3513 static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) in vlv_display_irq_uninstall() argument
3517 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_irq_uninstall()
3518 if (dev_priv->display_irqs_enabled) in vlv_display_irq_uninstall()
3519 valleyview_display_irqs_uninstall(dev_priv); in vlv_display_irq_uninstall()
3520 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_irq_uninstall()
3522 vlv_display_irq_reset(dev_priv); in vlv_display_irq_uninstall()
3524 dev_priv->irq_mask = ~0; in vlv_display_irq_uninstall()
3529 struct drm_i915_private *dev_priv = dev->dev_private; in valleyview_irq_uninstall() local
3531 if (!dev_priv) in valleyview_irq_uninstall()
3540 vlv_display_irq_uninstall(dev_priv); in valleyview_irq_uninstall()
3545 struct drm_i915_private *dev_priv = dev->dev_private; in cherryview_irq_uninstall() local
3547 if (!dev_priv) in cherryview_irq_uninstall()
3553 gen8_gt_irq_reset(dev_priv); in cherryview_irq_uninstall()
3557 vlv_display_irq_uninstall(dev_priv); in cherryview_irq_uninstall()
3562 struct drm_i915_private *dev_priv = dev->dev_private; in ironlake_irq_uninstall() local
3564 if (!dev_priv) in ironlake_irq_uninstall()
3572 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_preinstall() local
3575 for_each_pipe(dev_priv, pipe) in i8xx_irq_preinstall()
3584 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_postinstall() local
3590 dev_priv->irq_mask = in i8xx_irq_postinstall()
3595 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_irq_postinstall()
3605 spin_lock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3606 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3607 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
3608 spin_unlock_irq(&dev_priv->irq_lock); in i8xx_irq_postinstall()
3619 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_handle_vblank() local
3649 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_handler() local
3657 if (!intel_irqs_enabled(dev_priv)) in i8xx_irq_handler()
3670 spin_lock(&dev_priv->irq_lock); in i8xx_irq_handler()
3674 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3684 spin_unlock(&dev_priv->irq_lock); in i8xx_irq_handler()
3690 notify_ring(dev, &dev_priv->ring[RCS]); in i8xx_irq_handler()
3692 for_each_pipe(dev_priv, pipe) { in i8xx_irq_handler()
3705 intel_cpu_fifo_underrun_irq_handler(dev_priv, in i8xx_irq_handler()
3717 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_irq_uninstall() local
3720 for_each_pipe(dev_priv, pipe) { in i8xx_irq_uninstall()
3732 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_preinstall() local
3741 for_each_pipe(dev_priv, pipe) in i915_irq_preinstall()
3750 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_postinstall() local
3756 dev_priv->irq_mask = in i915_irq_postinstall()
3776 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; in i915_irq_postinstall()
3779 I915_WRITE(IMR, dev_priv->irq_mask); in i915_irq_postinstall()
3787 spin_lock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
3788 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3789 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
3790 spin_unlock_irq(&dev_priv->irq_lock); in i915_irq_postinstall()
3801 struct drm_i915_private *dev_priv = dev->dev_private; in i915_handle_vblank() local
3831 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_handler() local
3838 if (!intel_irqs_enabled(dev_priv)) in i915_irq_handler()
3851 spin_lock(&dev_priv->irq_lock); in i915_irq_handler()
3855 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
3865 spin_unlock(&dev_priv->irq_lock); in i915_irq_handler()
3879 notify_ring(dev, &dev_priv->ring[RCS]); in i915_irq_handler()
3881 for_each_pipe(dev_priv, pipe) { in i915_irq_handler()
3897 intel_cpu_fifo_underrun_irq_handler(dev_priv, in i915_irq_handler()
3928 struct drm_i915_private *dev_priv = dev->dev_private; in i915_irq_uninstall() local
3937 for_each_pipe(dev_priv, pipe) { in i915_irq_uninstall()
3950 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_preinstall() local
3957 for_each_pipe(dev_priv, pipe) in i965_irq_preinstall()
3966 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_postinstall() local
3971 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | in i965_irq_postinstall()
3979 enable_mask = ~dev_priv->irq_mask; in i965_irq_postinstall()
3989 spin_lock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
3990 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
3991 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
3992 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
3993 spin_unlock_irq(&dev_priv->irq_lock); in i965_irq_postinstall()
4010 I915_WRITE(IMR, dev_priv->irq_mask); in i965_irq_postinstall()
4024 struct drm_i915_private *dev_priv = dev->dev_private; in i915_hpd_irq_setup() local
4028 assert_spin_locked(&dev_priv->irq_lock); in i915_hpd_irq_setup()
4035 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) in i915_hpd_irq_setup()
4053 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_handler() local
4061 if (!intel_irqs_enabled(dev_priv)) in i965_irq_handler()
4075 spin_lock(&dev_priv->irq_lock); in i965_irq_handler()
4079 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4091 spin_unlock(&dev_priv->irq_lock); in i965_irq_handler()
4106 notify_ring(dev, &dev_priv->ring[RCS]); in i965_irq_handler()
4108 notify_ring(dev, &dev_priv->ring[VCS]); in i965_irq_handler()
4110 for_each_pipe(dev_priv, pipe) { in i965_irq_handler()
4122 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_irq_handler()
4154 struct drm_i915_private *dev_priv = dev->dev_private; in i965_irq_uninstall() local
4157 if (!dev_priv) in i965_irq_uninstall()
4164 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4169 for_each_pipe(dev_priv, pipe) in i965_irq_uninstall()
4177 struct drm_i915_private *dev_priv = in intel_hpd_irq_reenable_work() local
4178 container_of(work, typeof(*dev_priv), in intel_hpd_irq_reenable_work()
4180 struct drm_device *dev = dev_priv->dev; in intel_hpd_irq_reenable_work()
4184 intel_runtime_pm_get(dev_priv); in intel_hpd_irq_reenable_work()
4186 spin_lock_irq(&dev_priv->irq_lock); in intel_hpd_irq_reenable_work()
4190 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) in intel_hpd_irq_reenable_work()
4193 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; in intel_hpd_irq_reenable_work()
4208 if (dev_priv->display.hpd_irq_setup) in intel_hpd_irq_reenable_work()
4209 dev_priv->display.hpd_irq_setup(dev); in intel_hpd_irq_reenable_work()
4210 spin_unlock_irq(&dev_priv->irq_lock); in intel_hpd_irq_reenable_work()
4212 intel_runtime_pm_put(dev_priv); in intel_hpd_irq_reenable_work()
4222 void intel_irq_init(struct drm_i915_private *dev_priv) in intel_irq_init() argument
4224 struct drm_device *dev = dev_priv->dev; in intel_irq_init()
4226 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); in intel_irq_init()
4227 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func); in intel_irq_init()
4228 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); in intel_irq_init()
4229 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); in intel_irq_init()
4232 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) in intel_irq_init()
4234 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; in intel_irq_init()
4236 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; in intel_irq_init()
4238 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, in intel_irq_init()
4240 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work, in intel_irq_init()
4243 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); in intel_irq_init()
4245 if (IS_GEN2(dev_priv)) { in intel_irq_init()
4248 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { in intel_irq_init()
4261 if (!IS_GEN2(dev_priv)) in intel_irq_init()
4267 if (IS_CHERRYVIEW(dev_priv)) { in intel_irq_init()
4274 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4275 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_irq_init()
4282 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4283 } else if (INTEL_INFO(dev_priv)->gen >= 8) { in intel_irq_init()
4290 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; in intel_irq_init()
4298 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; in intel_irq_init()
4300 if (INTEL_INFO(dev_priv)->gen == 2) { in intel_irq_init()
4305 } else if (INTEL_INFO(dev_priv)->gen == 3) { in intel_irq_init()
4316 if (I915_HAS_HOTPLUG(dev_priv)) in intel_irq_init()
4317 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; in intel_irq_init()
4335 void intel_hpd_init(struct drm_i915_private *dev_priv) in intel_hpd_init() argument
4337 struct drm_device *dev = dev_priv->dev; in intel_hpd_init()
4343 dev_priv->hpd_stats[i].hpd_cnt = 0; in intel_hpd_init()
4344 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; in intel_hpd_init()
4357 spin_lock_irq(&dev_priv->irq_lock); in intel_hpd_init()
4358 if (dev_priv->display.hpd_irq_setup) in intel_hpd_init()
4359 dev_priv->display.hpd_irq_setup(dev); in intel_hpd_init()
4360 spin_unlock_irq(&dev_priv->irq_lock); in intel_hpd_init()
4374 int intel_irq_install(struct drm_i915_private *dev_priv) in intel_irq_install() argument
4381 dev_priv->pm.irqs_enabled = true; in intel_irq_install()
4383 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); in intel_irq_install()
4393 void intel_irq_uninstall(struct drm_i915_private *dev_priv) in intel_irq_uninstall() argument
4395 drm_irq_uninstall(dev_priv->dev); in intel_irq_uninstall()
4396 intel_hpd_cancel_work(dev_priv); in intel_irq_uninstall()
4397 dev_priv->pm.irqs_enabled = false; in intel_irq_uninstall()
4407 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_disable_interrupts() argument
4409 dev_priv->dev->driver->irq_uninstall(dev_priv->dev); in intel_runtime_pm_disable_interrupts()
4410 dev_priv->pm.irqs_enabled = false; in intel_runtime_pm_disable_interrupts()
4411 synchronize_irq(dev_priv->dev->irq); in intel_runtime_pm_disable_interrupts()
4421 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) in intel_runtime_pm_enable_interrupts() argument
4423 dev_priv->pm.irqs_enabled = true; in intel_runtime_pm_enable_interrupts()
4424 dev_priv->dev->driver->irq_preinstall(dev_priv->dev); in intel_runtime_pm_enable_interrupts()
4425 dev_priv->dev->driver->irq_postinstall(dev_priv->dev); in intel_runtime_pm_enable_interrupts()