586 				struct intel_engine_cs *ring,  in i915_gem_execbuffer_reserve_vma()  argument
683 i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,  in i915_gem_execbuffer_reserve()  argument
691 	bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;  in i915_gem_execbuffer_reserve()
694 	i915_gem_retire_requests_ring(ring);  in i915_gem_execbuffer_reserve()
749 				ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);  in i915_gem_execbuffer_reserve()
759 			ret = i915_gem_execbuffer_reserve_vma(vma, ring, need_relocs);  in i915_gem_execbuffer_reserve()
782 				  struct intel_engine_cs *ring,  in i915_gem_execbuffer_relocate_slow()  argument
870 	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);  in i915_gem_execbuffer_relocate_slow()
895 i915_gem_execbuffer_move_to_gpu(struct intel_engine_cs *ring,  in i915_gem_execbuffer_move_to_gpu()  argument
905 		ret = i915_gem_object_sync(obj, ring);  in i915_gem_execbuffer_move_to_gpu()
916 		i915_gem_chipset_flush(ring->dev);  in i915_gem_execbuffer_move_to_gpu()
924 	return intel_ring_invalidate_all_caches(ring);  in i915_gem_execbuffer_move_to_gpu()
986 			  struct intel_engine_cs *ring, const u32 ctx_id)  in i915_gem_validate_context()  argument
991 	if (ring->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)  in i915_gem_validate_context()
1004 	if (i915.enable_execlists && !ctx->engine[ring->id].state) {  in i915_gem_validate_context()
1005 		int ret = intel_lr_context_deferred_create(ctx, ring);  in i915_gem_validate_context()
1017 				   struct intel_engine_cs *ring)  in i915_gem_execbuffer_move_to_active()  argument
1019 	struct drm_i915_gem_request *req = intel_ring_get_request(ring);  in i915_gem_execbuffer_move_to_active()
1034 		i915_vma_move_to_active(vma, ring);  in i915_gem_execbuffer_move_to_active()
1038 			intel_fb_obj_invalidate(obj, ring, ORIGIN_CS);  in i915_gem_execbuffer_move_to_active()
1046 				struct drm_i915_private *dev_priv = to_i915(ring->dev);  in i915_gem_execbuffer_move_to_active()
1059 				    struct intel_engine_cs *ring,  in i915_gem_execbuffer_retire_commands()  argument
1063 	ring->gpu_caches_dirty = true;  in i915_gem_execbuffer_retire_commands()
1066 	(void)__i915_add_request(ring, file, obj);  in i915_gem_execbuffer_retire_commands()
1071 			    struct intel_engine_cs *ring)  in i915_reset_gen7_sol_offsets()  argument
1076 	if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {  in i915_reset_gen7_sol_offsets()
1081 	ret = intel_ring_begin(ring, 4 * 3);  in i915_reset_gen7_sol_offsets()
1086 		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));  in i915_reset_gen7_sol_offsets()
1087 		intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));  in i915_reset_gen7_sol_offsets()
1088 		intel_ring_emit(ring, 0);  in i915_reset_gen7_sol_offsets()
1091 	intel_ring_advance(ring);  in i915_reset_gen7_sol_offsets()
1097 i915_emit_box(struct intel_engine_cs *ring,  in i915_emit_box()  argument
1110 	if (INTEL_INFO(ring->dev)->gen >= 4) {  in i915_emit_box()
1111 		ret = intel_ring_begin(ring, 4);  in i915_emit_box()
1115 		intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);  in i915_emit_box()
1116 		intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);  in i915_emit_box()
1117 		intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);  in i915_emit_box()
1118 		intel_ring_emit(ring, DR4);  in i915_emit_box()
1120 		ret = intel_ring_begin(ring, 6);  in i915_emit_box()
1124 		intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);  in i915_emit_box()
1125 		intel_ring_emit(ring, DR1);  in i915_emit_box()
1126 		intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);  in i915_emit_box()
1127 		intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);  in i915_emit_box()
1128 		intel_ring_emit(ring, DR4);  in i915_emit_box()
1129 		intel_ring_emit(ring, 0);  in i915_emit_box()
1131 	intel_ring_advance(ring);  in i915_emit_box()
1137 i915_gem_execbuffer_parse(struct intel_engine_cs *ring,  in i915_gem_execbuffer_parse()  argument
1155 	ret = i915_parse_cmds(ring,  in i915_gem_execbuffer_parse()
1189 			       struct intel_engine_cs *ring,  in i915_gem_ringbuffer_submission()  argument
1204 		if (ring != &dev_priv->ring[RCS]) {  in i915_gem_ringbuffer_submission()
1246 	ret = i915_gem_execbuffer_move_to_gpu(ring, vmas);  in i915_gem_ringbuffer_submission()
1250 	ret = i915_switch_context(ring, ctx);  in i915_gem_ringbuffer_submission()
1255 		WARN(ctx->ppgtt->pd_dirty_rings & (1<<ring->id),  in i915_gem_ringbuffer_submission()
1256 			"%s didn't clear reload\n", ring->name);  in i915_gem_ringbuffer_submission()
1259 			(1<<ring->id), "%s didn't clear reload\n", ring->name);  in i915_gem_ringbuffer_submission()
1267 		if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {  in i915_gem_ringbuffer_submission()
1298 	if (ring == &dev_priv->ring[RCS] &&  in i915_gem_ringbuffer_submission()
1300 		ret = intel_ring_begin(ring, 4);  in i915_gem_ringbuffer_submission()
1304 		intel_ring_emit(ring, MI_NOOP);  in i915_gem_ringbuffer_submission()
1305 		intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));  in i915_gem_ringbuffer_submission()
1306 		intel_ring_emit(ring, INSTPM);  in i915_gem_ringbuffer_submission()
1307 		intel_ring_emit(ring, instp_mask << 16 | instp_mode);  in i915_gem_ringbuffer_submission()
1308 		intel_ring_advance(ring);  in i915_gem_ringbuffer_submission()
1314 		ret = i915_reset_gen7_sol_offsets(dev, ring);  in i915_gem_ringbuffer_submission()
1322 			ret = i915_emit_box(ring, &cliprects[i],  in i915_gem_ringbuffer_submission()
1327 			ret = ring->dispatch_execbuffer(ring,  in i915_gem_ringbuffer_submission()
1334 		ret = ring->dispatch_execbuffer(ring,  in i915_gem_ringbuffer_submission()
1341 	trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags);  in i915_gem_ringbuffer_submission()
1343 	i915_gem_execbuffer_move_to_active(vmas, ring);  in i915_gem_ringbuffer_submission()
1344 	i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);  in i915_gem_ringbuffer_submission()
1376 		file_priv->bsd_ring = &dev_priv->ring[ring_id];  in gen8_dispatch_bsd_ring()
1411 	struct intel_engine_cs *ring;  in i915_gem_do_execbuffer()  local
1451 		ring = &dev_priv->ring[RCS];  in i915_gem_do_execbuffer()
1459 				ring = &dev_priv->ring[ring_id];  in i915_gem_do_execbuffer()
1462 				ring = &dev_priv->ring[VCS];  in i915_gem_do_execbuffer()
1465 				ring = &dev_priv->ring[VCS2];  in i915_gem_do_execbuffer()
1473 			ring = &dev_priv->ring[VCS];  in i915_gem_do_execbuffer()
1475 		ring = &dev_priv->ring[(args->flags & I915_EXEC_RING_MASK) - 1];  in i915_gem_do_execbuffer()
1477 	if (!intel_ring_initialized(ring)) {  in i915_gem_do_execbuffer()
1494 	ctx = i915_gem_validate_context(dev, file, ring, ctx_id);  in i915_gem_do_execbuffer()
1526 	ret = i915_gem_execbuffer_reserve(ring, &eb->vmas, &need_relocs);  in i915_gem_do_execbuffer()
1535 			ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,  in i915_gem_do_execbuffer()
1550 	if (i915_needs_cmd_parser(ring) && args->batch_len) {  in i915_gem_do_execbuffer()
1551 		batch_obj = i915_gem_execbuffer_parse(ring,  in i915_gem_do_execbuffer()
1604 	ret = dev_priv->gt.do_execbuf(dev, file, ring, ctx, args,  in i915_gem_do_execbuffer()