436 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_detect_pch()  local
443 		dev_priv->pch_type = PCH_NOP;  in intel_detect_pch()
461 			dev_priv->pch_id = id;  in intel_detect_pch()
464 				dev_priv->pch_type = PCH_IBX;  in intel_detect_pch()
468 				dev_priv->pch_type = PCH_CPT;  in intel_detect_pch()
473 				dev_priv->pch_type = PCH_CPT;  in intel_detect_pch()
477 				dev_priv->pch_type = PCH_LPT;  in intel_detect_pch()
482 				dev_priv->pch_type = PCH_LPT;  in intel_detect_pch()
487 				dev_priv->pch_type = PCH_SPT;  in intel_detect_pch()
491 				dev_priv->pch_type = PCH_SPT;  in intel_detect_pch()
531 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)  in intel_hpd_cancel_work()  argument
533 	spin_lock_irq(&dev_priv->irq_lock);  in intel_hpd_cancel_work()
535 	dev_priv->long_hpd_port_mask = 0;  in intel_hpd_cancel_work()
536 	dev_priv->short_hpd_port_mask = 0;  in intel_hpd_cancel_work()
537 	dev_priv->hpd_event_bits = 0;  in intel_hpd_cancel_work()
539 	spin_unlock_irq(&dev_priv->irq_lock);  in intel_hpd_cancel_work()
541 	cancel_work_sync(&dev_priv->dig_port_work);  in intel_hpd_cancel_work()
542 	cancel_work_sync(&dev_priv->hotplug_work);  in intel_hpd_cancel_work()
543 	cancel_delayed_work_sync(&dev_priv->hotplug_reenable_work);  in intel_hpd_cancel_work()
546 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)  in intel_suspend_encoders()  argument
548 	struct drm_device *dev = dev_priv->dev;  in intel_suspend_encoders()
561 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
562 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
567 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drm_suspend()  local
573 	mutex_lock(&dev_priv->modeset_restore_lock);  in i915_drm_suspend()
574 	dev_priv->modeset_restore = MODESET_SUSPENDED;  in i915_drm_suspend()
575 	mutex_unlock(&dev_priv->modeset_restore_lock);  in i915_drm_suspend()
579 	intel_display_set_init_power(dev_priv, true);  in i915_drm_suspend()
605 	intel_runtime_pm_disable_interrupts(dev_priv);  in i915_drm_suspend()
606 	intel_hpd_cancel_work(dev_priv);  in i915_drm_suspend()
608 	intel_suspend_encoders(dev_priv);  in i915_drm_suspend()
628 	dev_priv->suspend_count++;  in i915_drm_suspend()
630 	intel_display_set_init_power(dev_priv, false);  in i915_drm_suspend()
637 	struct drm_i915_private *dev_priv = drm_dev->dev_private;  in i915_drm_suspend_late()  local
640 	ret = intel_suspend_complete(dev_priv);  in i915_drm_suspend_late()
661 	if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))  in i915_drm_suspend_late()
693 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drm_resume()  local
713 	intel_runtime_pm_enable_interrupts(dev_priv);  in i915_drm_resume()
718 		atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);  in i915_drm_resume()
724 	spin_lock_irq(&dev_priv->irq_lock);  in i915_drm_resume()
725 	if (dev_priv->display.hpd_irq_setup)  in i915_drm_resume()
726 		dev_priv->display.hpd_irq_setup(dev);  in i915_drm_resume()
727 	spin_unlock_irq(&dev_priv->irq_lock);  in i915_drm_resume()
741 	intel_hpd_init(dev_priv);  in i915_drm_resume()
749 	mutex_lock(&dev_priv->modeset_restore_lock);  in i915_drm_resume()
750 	dev_priv->modeset_restore = MODESET_DONE;  in i915_drm_resume()
751 	mutex_unlock(&dev_priv->modeset_restore_lock);  in i915_drm_resume()
762 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drm_resume_early()  local
779 	if (IS_VALLEYVIEW(dev_priv))  in i915_drm_resume_early()
780 		ret = vlv_resume_prepare(dev_priv, false);  in i915_drm_resume_early()
786 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in i915_drm_resume_early()
787 		hsw_disable_pc8(dev_priv);  in i915_drm_resume_early()
790 	intel_power_domains_init_hw(dev_priv);  in i915_drm_resume_early()
826 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_reset()  local
839 	simulated = dev_priv->gpu_error.stop_rings != 0;  in i915_reset()
846 		dev_priv->gpu_error.stop_rings = 0;  in i915_reset()
854 	if (i915_stop_ring_allow_warn(dev_priv))  in i915_reset()
863 	intel_overlay_reset(dev_priv);  in i915_reset()
881 	dev_priv->gpu_error.reload_in_reset = true;  in i915_reset()
885 	dev_priv->gpu_error.reload_in_reset = false;  in i915_reset()
1002 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)  in hsw_suspend_complete()  argument
1004 	hsw_enable_pc8(dev_priv);  in hsw_suspend_complete()
1035 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)  in vlv_save_gunit_s0ix_state()  argument
1037 	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;  in vlv_save_gunit_s0ix_state()
1116 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)  in vlv_restore_gunit_s0ix_state()  argument
1118 	struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;  in vlv_restore_gunit_s0ix_state()
1203 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)  in vlv_force_gfx_clock()  argument
1228 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)  in vlv_allow_gt_wake()  argument
1249 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,  in vlv_wait_for_gt_wells()  argument
1279 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)  in vlv_check_no_gt_access()  argument
1288 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)  in vlv_suspend_complete()  argument
1297 	(void)vlv_wait_for_gt_wells(dev_priv, false);  in vlv_suspend_complete()
1302 	vlv_check_no_gt_access(dev_priv);  in vlv_suspend_complete()
1304 	err = vlv_force_gfx_clock(dev_priv, true);  in vlv_suspend_complete()
1308 	err = vlv_allow_gt_wake(dev_priv, false);  in vlv_suspend_complete()
1312 	if (!IS_CHERRYVIEW(dev_priv->dev))  in vlv_suspend_complete()
1313 		vlv_save_gunit_s0ix_state(dev_priv);  in vlv_suspend_complete()
1315 	err = vlv_force_gfx_clock(dev_priv, false);  in vlv_suspend_complete()
1323 	vlv_allow_gt_wake(dev_priv, true);  in vlv_suspend_complete()
1325 	vlv_force_gfx_clock(dev_priv, false);  in vlv_suspend_complete()
1330 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,  in vlv_resume_prepare()  argument
1333 	struct drm_device *dev = dev_priv->dev;  in vlv_resume_prepare()
1342 	ret = vlv_force_gfx_clock(dev_priv, true);  in vlv_resume_prepare()
1344 	if (!IS_CHERRYVIEW(dev_priv->dev))  in vlv_resume_prepare()
1345 		vlv_restore_gunit_s0ix_state(dev_priv);  in vlv_resume_prepare()
1347 	err = vlv_allow_gt_wake(dev_priv, true);  in vlv_resume_prepare()
1351 	err = vlv_force_gfx_clock(dev_priv, false);  in vlv_resume_prepare()
1355 	vlv_check_no_gt_access(dev_priv);  in vlv_resume_prepare()
1369 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_runtime_suspend()  local
1372 	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))  in intel_runtime_suspend()
1401 	i915_gem_release_all_mmaps(dev_priv);  in intel_runtime_suspend()
1405 	intel_runtime_pm_disable_interrupts(dev_priv);  in intel_runtime_suspend()
1407 	ret = intel_suspend_complete(dev_priv);  in intel_runtime_suspend()
1410 		intel_runtime_pm_enable_interrupts(dev_priv);  in intel_runtime_suspend()
1415 	cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);  in intel_runtime_suspend()
1417 	dev_priv->pm.suspended = true;  in intel_runtime_suspend()
1444 	assert_forcewakes_inactive(dev_priv);  in intel_runtime_suspend()
1454 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_runtime_resume()  local
1463 	dev_priv->pm.suspended = false;  in intel_runtime_resume()
1465 	if (IS_GEN6(dev_priv))  in intel_runtime_resume()
1467 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_runtime_resume()
1468 		hsw_disable_pc8(dev_priv);  in intel_runtime_resume()
1469 	else if (IS_VALLEYVIEW(dev_priv))  in intel_runtime_resume()
1470 		ret = vlv_resume_prepare(dev_priv, true);  in intel_runtime_resume()
1479 	intel_runtime_pm_enable_interrupts(dev_priv);  in intel_runtime_resume()
1494 static int intel_suspend_complete(struct drm_i915_private *dev_priv)  in intel_suspend_complete()  argument
1496 	struct drm_device *dev = dev_priv->dev;  in intel_suspend_complete()
1500 		ret = hsw_suspend_complete(dev_priv);  in intel_suspend_complete()
1502 		ret = vlv_suspend_complete(dev_priv);  in intel_suspend_complete()