Lines Matching refs:seq_printf
86 seq_printf(m, "gen: %d\n", info->gen); in i915_capabilities()
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev)); in i915_capabilities()
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x)) in i915_capabilities()
126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %x %x %x%s%s%s", in describe_obj()
141 seq_printf(m, " (name: %d)", obj->base.name); in describe_obj()
146 seq_printf(m, " (pinned x %d)", pin_count); in describe_obj()
148 seq_printf(m, " (display)"); in describe_obj()
150 seq_printf(m, " (fence: %d)", obj->fence_reg); in describe_obj()
156 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)", in describe_obj()
161 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); in describe_obj()
169 seq_printf(m, " (%s mappable)", s); in describe_obj()
172 seq_printf(m, " (%s)", in describe_obj()
175 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits); in describe_obj()
218 seq_printf(m, " "); in i915_gem_object_list_info()
220 seq_printf(m, "\n"); in i915_gem_object_list_info()
227 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", in i915_gem_object_list_info()
288 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", in i915_gem_stolen_list_info()
365 …seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu un…
419 seq_printf(m, "%u objects, %zu bytes\n", in i915_gem_object_info()
425 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n", in i915_gem_object_info()
430 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n", in i915_gem_object_info()
435 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n", in i915_gem_object_info()
444 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size); in i915_gem_object_info()
461 seq_printf(m, "%u purgeable objects, %zu bytes\n", in i915_gem_object_info()
463 seq_printf(m, "%u pinned mappable objects, %zu bytes\n", in i915_gem_object_info()
465 seq_printf(m, "%u fault mappable objects, %zu bytes\n", in i915_gem_object_info()
468 seq_printf(m, "%zu [%lu] gtt total\n", in i915_gem_object_info()
531 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n", in i915_gem_gtt_info()
557 seq_printf(m, "No flip due on pipe %c (plane %c)\n", in i915_gem_pageflip_info()
563 seq_printf(m, "Flip queued on pipe %c (plane %c)\n", in i915_gem_pageflip_info()
566 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n", in i915_gem_pageflip_info()
573 …seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d… in i915_gem_pageflip_info()
580 seq_printf(m, "Flip not associated with any ring\n"); in i915_gem_pageflip_info()
581 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n", in i915_gem_pageflip_info()
589 seq_printf(m, "%d prepares\n", atomic_read(&work->pending)); in i915_gem_pageflip_info()
595 seq_printf(m, "Current scanout address 0x%08x\n", addr); in i915_gem_pageflip_info()
598 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset); in i915_gem_pageflip_info()
599 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset); in i915_gem_pageflip_info()
633 seq_printf(m, "total: %d\n", count); in i915_gem_batch_pool_info()
658 seq_printf(m, "%s requests:\n", ring->name); in i915_gem_request_info()
662 seq_printf(m, " %x @ %d\n", in i915_gem_request_info()
680 seq_printf(m, "Current sequence (%s): %x\n", in i915_ring_seqno_info()
722 seq_printf(m, "Master Interrupt Control:\t%08x\n", in i915_interrupt_info()
725 seq_printf(m, "Display IER:\t%08x\n", in i915_interrupt_info()
727 seq_printf(m, "Display IIR:\t%08x\n", in i915_interrupt_info()
729 seq_printf(m, "Display IIR_RW:\t%08x\n", in i915_interrupt_info()
731 seq_printf(m, "Display IMR:\t%08x\n", in i915_interrupt_info()
734 seq_printf(m, "Pipe %c stat:\t%08x\n", in i915_interrupt_info()
738 seq_printf(m, "Port hotplug:\t%08x\n", in i915_interrupt_info()
740 seq_printf(m, "DPFLIPSTAT:\t%08x\n", in i915_interrupt_info()
742 seq_printf(m, "DPINVGTT:\t%08x\n", in i915_interrupt_info()
746 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", in i915_interrupt_info()
748 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", in i915_interrupt_info()
750 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", in i915_interrupt_info()
754 seq_printf(m, "PCU interrupt mask:\t%08x\n", in i915_interrupt_info()
756 seq_printf(m, "PCU interrupt identity:\t%08x\n", in i915_interrupt_info()
758 seq_printf(m, "PCU interrupt enable:\t%08x\n", in i915_interrupt_info()
761 seq_printf(m, "Master Interrupt Control:\t%08x\n", in i915_interrupt_info()
765 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", in i915_interrupt_info()
767 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", in i915_interrupt_info()
769 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", in i915_interrupt_info()
776 seq_printf(m, "Pipe %c power disabled\n", in i915_interrupt_info()
780 seq_printf(m, "Pipe %c IMR:\t%08x\n", in i915_interrupt_info()
783 seq_printf(m, "Pipe %c IIR:\t%08x\n", in i915_interrupt_info()
786 seq_printf(m, "Pipe %c IER:\t%08x\n", in i915_interrupt_info()
791 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", in i915_interrupt_info()
793 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", in i915_interrupt_info()
795 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", in i915_interrupt_info()
798 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", in i915_interrupt_info()
800 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", in i915_interrupt_info()
802 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", in i915_interrupt_info()
805 seq_printf(m, "PCU interrupt mask:\t%08x\n", in i915_interrupt_info()
807 seq_printf(m, "PCU interrupt identity:\t%08x\n", in i915_interrupt_info()
809 seq_printf(m, "PCU interrupt enable:\t%08x\n", in i915_interrupt_info()
812 seq_printf(m, "Display IER:\t%08x\n", in i915_interrupt_info()
814 seq_printf(m, "Display IIR:\t%08x\n", in i915_interrupt_info()
816 seq_printf(m, "Display IIR_RW:\t%08x\n", in i915_interrupt_info()
818 seq_printf(m, "Display IMR:\t%08x\n", in i915_interrupt_info()
821 seq_printf(m, "Pipe %c stat:\t%08x\n", in i915_interrupt_info()
825 seq_printf(m, "Master IER:\t%08x\n", in i915_interrupt_info()
828 seq_printf(m, "Render IER:\t%08x\n", in i915_interrupt_info()
830 seq_printf(m, "Render IIR:\t%08x\n", in i915_interrupt_info()
832 seq_printf(m, "Render IMR:\t%08x\n", in i915_interrupt_info()
835 seq_printf(m, "PM IER:\t\t%08x\n", in i915_interrupt_info()
837 seq_printf(m, "PM IIR:\t\t%08x\n", in i915_interrupt_info()
839 seq_printf(m, "PM IMR:\t\t%08x\n", in i915_interrupt_info()
842 seq_printf(m, "Port hotplug:\t%08x\n", in i915_interrupt_info()
844 seq_printf(m, "DPFLIPSTAT:\t%08x\n", in i915_interrupt_info()
846 seq_printf(m, "DPINVGTT:\t%08x\n", in i915_interrupt_info()
850 seq_printf(m, "Interrupt enable: %08x\n", in i915_interrupt_info()
852 seq_printf(m, "Interrupt identity: %08x\n", in i915_interrupt_info()
854 seq_printf(m, "Interrupt mask: %08x\n", in i915_interrupt_info()
857 seq_printf(m, "Pipe %c stat: %08x\n", in i915_interrupt_info()
861 seq_printf(m, "North Display Interrupt enable: %08x\n", in i915_interrupt_info()
863 seq_printf(m, "North Display Interrupt identity: %08x\n", in i915_interrupt_info()
865 seq_printf(m, "North Display Interrupt mask: %08x\n", in i915_interrupt_info()
867 seq_printf(m, "South Display Interrupt enable: %08x\n", in i915_interrupt_info()
869 seq_printf(m, "South Display Interrupt identity: %08x\n", in i915_interrupt_info()
871 seq_printf(m, "South Display Interrupt mask: %08x\n", in i915_interrupt_info()
873 seq_printf(m, "Graphics Interrupt enable: %08x\n", in i915_interrupt_info()
875 seq_printf(m, "Graphics Interrupt identity: %08x\n", in i915_interrupt_info()
877 seq_printf(m, "Graphics Interrupt mask: %08x\n", in i915_interrupt_info()
882 seq_printf(m, in i915_interrupt_info()
905 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); in i915_gem_fence_regs_info()
906 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); in i915_gem_fence_regs_info()
910 seq_printf(m, "Fence %d, pin count = %d, object = ", in i915_gem_fence_regs_info()
938 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n", in i915_hws_info()
1086 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); in i915_frequency_info()
1087 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); in i915_frequency_info()
1088 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> in i915_frequency_info()
1090 seq_printf(m, "Current P-state: %d\n", in i915_frequency_info()
1158 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n", in i915_frequency_info()
1160 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); in i915_frequency_info()
1161 seq_printf(m, "Render p-state ratio: %d\n", in i915_frequency_info()
1163 seq_printf(m, "Render p-state VID: %d\n", in i915_frequency_info()
1165 seq_printf(m, "Render p-state limit: %d\n", in i915_frequency_info()
1167 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); in i915_frequency_info()
1168 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); in i915_frequency_info()
1169 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); in i915_frequency_info()
1170 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); in i915_frequency_info()
1171 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); in i915_frequency_info()
1172 seq_printf(m, "CAGF: %dMHz\n", cagf); in i915_frequency_info()
1173 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei & in i915_frequency_info()
1175 seq_printf(m, "RP CUR UP: %dus\n", rpcurup & in i915_frequency_info()
1177 seq_printf(m, "RP PREV UP: %dus\n", rpprevup & in i915_frequency_info()
1179 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei & in i915_frequency_info()
1181 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown & in i915_frequency_info()
1183 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown & in i915_frequency_info()
1188 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", in i915_frequency_info()
1193 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", in i915_frequency_info()
1198 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", in i915_frequency_info()
1201 seq_printf(m, "Max overclocked frequency: %dMHz\n", in i915_frequency_info()
1204 seq_printf(m, "Idle freq: %d MHz\n", in i915_frequency_info()
1211 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); in i915_frequency_info()
1212 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); in i915_frequency_info()
1214 seq_printf(m, "max GPU freq: %d MHz\n", in i915_frequency_info()
1217 seq_printf(m, "min GPU freq: %d MHz\n", in i915_frequency_info()
1220 seq_printf(m, "idle GPU freq: %d MHz\n", in i915_frequency_info()
1223 seq_printf(m, in i915_frequency_info()
1227 seq_printf(m, "current GPU freq: %d MHz\n", in i915_frequency_info()
1250 seq_printf(m, "Hangcheck disabled\n"); in i915_hangcheck_info()
1264 seq_printf(m, "Hangcheck active, fires in %dms\n", in i915_hangcheck_info()
1268 seq_printf(m, "Hangcheck inactive\n"); in i915_hangcheck_info()
1271 seq_printf(m, "%s:\n", ring->name); in i915_hangcheck_info()
1272 seq_printf(m, "\tseqno = %x [current %x]\n", in i915_hangcheck_info()
1274 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", in i915_hangcheck_info()
1277 seq_printf(m, "\tmax ACTHD = 0x%08llx\n", in i915_hangcheck_info()
1279 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score); in i915_hangcheck_info()
1280 seq_printf(m, "\taction = %d\n", ring->hangcheck.action); in i915_hangcheck_info()
1307 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ? in ironlake_drpc_info()
1309 seq_printf(m, "Boost freq: %d\n", in ironlake_drpc_info()
1312 seq_printf(m, "HW control enabled: %s\n", in ironlake_drpc_info()
1314 seq_printf(m, "SW control enabled: %s\n", in ironlake_drpc_info()
1316 seq_printf(m, "Gated voltage change: %s\n", in ironlake_drpc_info()
1318 seq_printf(m, "Starting frequency: P%d\n", in ironlake_drpc_info()
1320 seq_printf(m, "Max P-state: P%d\n", in ironlake_drpc_info()
1322 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); in ironlake_drpc_info()
1323 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); in ironlake_drpc_info()
1324 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); in ironlake_drpc_info()
1325 seq_printf(m, "Render standby enabled: %s\n", in ironlake_drpc_info()
1365 seq_printf(m, "%s.wake_count = %u\n", in i915_forcewake_domains()
1389 seq_printf(m, "Video Turbo Mode: %s\n", in vlv_drpc_info()
1391 seq_printf(m, "Turbo enabled: %s\n", in vlv_drpc_info()
1393 seq_printf(m, "HW control enabled: %s\n", in vlv_drpc_info()
1395 seq_printf(m, "SW control enabled: %s\n", in vlv_drpc_info()
1398 seq_printf(m, "RC6 Enabled: %s\n", in vlv_drpc_info()
1401 seq_printf(m, "Render Power Well: %s\n", in vlv_drpc_info()
1403 seq_printf(m, "Media Power Well: %s\n", in vlv_drpc_info()
1406 seq_printf(m, "Render RC6 residency since boot: %u\n", in vlv_drpc_info()
1408 seq_printf(m, "Media RC6 residency since boot: %u\n", in vlv_drpc_info()
1439 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51)); in gen6_drpc_info()
1454 seq_printf(m, "Video Turbo Mode: %s\n", in gen6_drpc_info()
1456 seq_printf(m, "HW control enabled: %s\n", in gen6_drpc_info()
1458 seq_printf(m, "SW control enabled: %s\n", in gen6_drpc_info()
1461 seq_printf(m, "RC1e Enabled: %s\n", in gen6_drpc_info()
1463 seq_printf(m, "RC6 Enabled: %s\n", in gen6_drpc_info()
1465 seq_printf(m, "Deep RC6 Enabled: %s\n", in gen6_drpc_info()
1467 seq_printf(m, "Deepest RC6 Enabled: %s\n", in gen6_drpc_info()
1491 seq_printf(m, "Core Power Down: %s\n", in gen6_drpc_info()
1495 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n", in gen6_drpc_info()
1497 seq_printf(m, "RC6 residency since boot: %u\n", in gen6_drpc_info()
1499 seq_printf(m, "RC6+ residency since boot: %u\n", in gen6_drpc_info()
1501 seq_printf(m, "RC6++ residency since boot: %u\n", in gen6_drpc_info()
1504 seq_printf(m, "RC6 voltage: %dmV\n", in gen6_drpc_info()
1506 seq_printf(m, "RC6+ voltage: %dmV\n", in gen6_drpc_info()
1508 seq_printf(m, "RC6++ voltage: %dmV\n", in gen6_drpc_info()
1642 seq_printf(m, "Enabled by kernel parameter: %s\n", in i915_ips_status()
1682 seq_printf(m, "self-refresh: %s\n", in i915_sr_status()
1708 seq_printf(m, "GMCH temp: %ld\n", temp); in i915_emon_status()
1709 seq_printf(m, "Chipset power: %ld\n", chipset); in i915_emon_status()
1710 seq_printf(m, "GFX power: %ld\n", gfx); in i915_emon_status()
1711 seq_printf(m, "Total power: %ld\n", chipset + gfx); in i915_emon_status()
1746 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", in i915_ring_freq_table()
1800 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", in i915_gem_framebuffer_info()
1816 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", in i915_gem_framebuffer_info()
1834 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)", in describe_ctx_ringbuf()
1861 seq_printf(m, "(default context %s) ", in i915_context_status()
1873 seq_printf(m, "%s: ", ring->name); in i915_context_status()
1902 seq_printf(m, "Context on %s with no gem object\n", in i915_dump_lrc_obj()
1907 seq_printf(m, "CONTEXT: %s %u\n", ring->name, in i915_dump_lrc_obj()
1925 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n", in i915_dump_lrc_obj()
1946 seq_printf(m, "Logical Ring Contexts are disabled\n"); in i915_dump_lrc()
1998 seq_printf(m, "%s\n", ring->name); in i915_execlists()
2002 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n", in i915_execlists()
2006 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer); in i915_execlists()
2012 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n", in i915_execlists()
2019 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n", in i915_execlists()
2030 seq_printf(m, "\t%d requests in queue\n", count); in i915_execlists()
2035 seq_printf(m, "\tHead request id: %u\n", in i915_execlists()
2037 seq_printf(m, "\tHead request tail: %u\n", in i915_execlists()
2086 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", in i915_swizzle_info()
2088 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", in i915_swizzle_info()
2092 seq_printf(m, "DDC = 0x%08x\n", in i915_swizzle_info()
2094 seq_printf(m, "DDC2 = 0x%08x\n", in i915_swizzle_info()
2096 seq_printf(m, "C0DRB3 = 0x%04x\n", in i915_swizzle_info()
2098 seq_printf(m, "C1DRB3 = 0x%04x\n", in i915_swizzle_info()
2101 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", in i915_swizzle_info()
2103 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", in i915_swizzle_info()
2105 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", in i915_swizzle_info()
2107 seq_printf(m, "TILECTL = 0x%08x\n", in i915_swizzle_info()
2110 seq_printf(m, "GAMTARBMODE = 0x%08x\n", in i915_swizzle_info()
2113 seq_printf(m, "ARB_MODE = 0x%08x\n", in i915_swizzle_info()
2115 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", in i915_swizzle_info()
2135 seq_printf(m, " no ppgtt for context %d\n", in per_file_ctx()
2143 seq_printf(m, " context %d:\n", ctx->user_handle); in per_file_ctx()
2159 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages); in gen8_ppgtt_info()
2160 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries); in gen8_ppgtt_info()
2162 seq_printf(m, "%s\n", ring->name); in gen8_ppgtt_info()
2168 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp); in gen8_ppgtt_info()
2181 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); in gen6_ppgtt_info()
2184 seq_printf(m, "%s\n", ring->name); in gen6_ppgtt_info()
2186 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring))); in gen6_ppgtt_info()
2187 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring))); in gen6_ppgtt_info()
2188 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring))); in gen6_ppgtt_info()
2189 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring))); in gen6_ppgtt_info()
2195 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset); in gen6_ppgtt_info()
2203 seq_printf(m, "proc: %s\n", in gen6_ppgtt_info()
2207 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK)); in gen6_ppgtt_info()
2239 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev))); in i915_llc()
2240 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size); in i915_llc()
2263 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); in i915_edp_psr_status()
2264 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); in i915_edp_psr_status()
2265 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); in i915_edp_psr_status()
2266 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); in i915_edp_psr_status()
2267 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n", in i915_edp_psr_status()
2269 seq_printf(m, "Re-enable work scheduled: %s\n", in i915_edp_psr_status()
2283 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled)); in i915_edp_psr_status()
2289 seq_printf(m, " pipe %c", pipe_name(pipe)); in i915_edp_psr_status()
2293 seq_printf(m, "Link standby: %s\n", in i915_edp_psr_status()
2301 seq_printf(m, "Performance_Counter: %u\n", psrperf); in i915_edp_psr_status()
2338 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n", in i915_sink_crc()
2370 seq_printf(m, "%llu", (long long unsigned)power); in i915_energy_uJ()
2386 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy)); in i915_pc8_status()
2387 seq_printf(m, "IRQs disabled: %s\n", in i915_pc8_status()
2470 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); in i915_power_domain_info()
2476 seq_printf(m, "%-25s %d\n", power_well->name, in i915_power_domain_info()
2484 seq_printf(m, " %-23s %d\n", in i915_power_domain_info()
2503 …seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d… in intel_seq_print_mode()
2524 seq_printf(m, "\tencoder %d: type: %s, connectors:\n", in intel_encoder_info()
2528 seq_printf(m, "\t\tconnector %d: type: %s, status: %s", in intel_encoder_info()
2534 seq_printf(m, ", mode:\n"); in intel_encoder_info()
2550 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", in intel_crtc_info()
2563 seq_printf(m, "\tfixed mode:\n"); in intel_panel_info()
2573 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_info()
2574 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" : in intel_dp_info()
2586 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" : in intel_hdmi_info()
2603 seq_printf(m, "connector %d: type %s, status: %s\n", in intel_connector_info()
2607 seq_printf(m, "\tname: %s\n", connector->display_info.name); in intel_connector_info()
2608 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", in intel_connector_info()
2611 seq_printf(m, "\tsubpixel order: %s\n", in intel_connector_info()
2613 seq_printf(m, "\tCEA rev: %d\n", in intel_connector_info()
2626 seq_printf(m, "\tmodes:\n"); in intel_connector_info()
2672 seq_printf(m, "CRTC info\n"); in i915_display_info()
2673 seq_printf(m, "---------\n"); in i915_display_info()
2678 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n", in i915_display_info()
2686 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n", in i915_display_info()
2693 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", in i915_display_info()
2698 seq_printf(m, "\n"); in i915_display_info()
2699 seq_printf(m, "Connector info\n"); in i915_display_info()
2700 seq_printf(m, "--------------\n"); in i915_display_info()
2739 seq_printf(m, "%s\n", ring->name); in i915_semaphore_status()
2744 seq_printf(m, "0x%08llx (0x%02llx) ", in i915_semaphore_status()
2752 seq_printf(m, "0x%08llx (0x%02llx) ", in i915_semaphore_status()
2763 seq_printf(m, "0x%08x\n", in i915_semaphore_status()
2771 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]); in i915_semaphore_status()
2793 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id); in i915_shared_dplls_info()
2794 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n", in i915_shared_dplls_info()
2796 seq_printf(m, " tracked hardware state:\n"); in i915_shared_dplls_info()
2797 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll); in i915_shared_dplls_info()
2798 seq_printf(m, " dpll_md: 0x%08x\n", in i915_shared_dplls_info()
2800 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0); in i915_shared_dplls_info()
2801 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1); in i915_shared_dplls_info()
2802 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll); in i915_shared_dplls_info()
2823 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count); in i915_wa_registers()
2833 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n", in i915_wa_registers()
2860 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); in i915_ddb_info()
2863 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); in i915_ddb_info()
2867 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1, in i915_ddb_info()
2873 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, in i915_ddb_info()
2906 seq_printf(m, "Other encoder (id=%d).\n", in drrs_status_per_crtc()
2938 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", in drrs_status_per_crtc()
2949 seq_printf(m, "DRRS_State: Unknown(%d)\n", in drrs_status_per_crtc()
2954 seq_printf(m, "\t\tVrefresh: %d", vrefresh); in drrs_status_per_crtc()
2977 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); in i915_drrs_status()
3211 seq_printf(m, "%c %s\n", pipe_name(i), in display_crc_ctl_show()
3892 seq_printf(m, "WM%d %u (%u.%u usec)\n", in wm_latency_show()
4487 seq_printf(m, " Available Slice Total: %u\n", in i915_sseu_status()
4489 seq_printf(m, " Available Subslice Total: %u\n", in i915_sseu_status()
4491 seq_printf(m, " Available Subslice Per Slice: %u\n", in i915_sseu_status()
4493 seq_printf(m, " Available EU Total: %u\n", in i915_sseu_status()
4495 seq_printf(m, " Available EU Per Subslice: %u\n", in i915_sseu_status()
4497 seq_printf(m, " Has Slice Power Gating: %s\n", in i915_sseu_status()
4499 seq_printf(m, " Has Subslice Power Gating: %s\n", in i915_sseu_status()
4501 seq_printf(m, " Has EU Power Gating: %s\n", in i915_sseu_status()
4573 seq_printf(m, " Enabled Slice Total: %u\n", s_tot); in i915_sseu_status()
4574 seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot); in i915_sseu_status()
4575 seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per); in i915_sseu_status()
4576 seq_printf(m, " Enabled EU Total: %u\n", eu_tot); in i915_sseu_status()
4577 seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per); in i915_sseu_status()