1080 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_frequency_info()
1202 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_frequency_info()
1205 			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));  in i915_frequency_info()
1209 		mutex_lock(&dev_priv->rps.hw_lock);  in i915_frequency_info()
1215 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_frequency_info()
1218 			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));  in i915_frequency_info()
1221 			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));  in i915_frequency_info()
1225 			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in i915_frequency_info()
1229 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_frequency_info()
1448 	mutex_lock(&dev_priv->rps.hw_lock);  in gen6_drpc_info()
1450 	mutex_unlock(&dev_priv->rps.hw_lock);  in gen6_drpc_info()
1731 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_ring_freq_table()
1733 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_ring_freq_table()
1739 	for (gpu_freq = dev_priv->rps.min_freq_softlimit;  in i915_ring_freq_table()
1740 	     gpu_freq <= dev_priv->rps.max_freq_softlimit;  in i915_ring_freq_table()
1752 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_ring_freq_table()
4296 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_max_freq_get()
4298 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_max_freq_get()
4302 	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);  in i915_max_freq_get()
4303 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_get()
4319 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_max_freq_set()
4323 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4332 	hw_max = dev_priv->rps.max_freq;  in i915_max_freq_set()
4333 	hw_min = dev_priv->rps.min_freq;  in i915_max_freq_set()
4335 	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {  in i915_max_freq_set()
4336 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4340 	dev_priv->rps.max_freq_softlimit = val;  in i915_max_freq_set()
4344 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4363 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_min_freq_get()
4365 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_min_freq_get()
4369 	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);  in i915_min_freq_get()
4370 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_get()
4386 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_min_freq_set()
4390 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4399 	hw_max = dev_priv->rps.max_freq;  in i915_min_freq_set()
4400 	hw_min = dev_priv->rps.min_freq;  in i915_min_freq_set()
4402 	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {  in i915_min_freq_set()
4403 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4407 	dev_priv->rps.min_freq_softlimit = val;  in i915_min_freq_set()
4411 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_set()