191 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_object_list_info()  local
192 	struct i915_address_space *vm = &dev_priv->gtt.base;  in i915_gem_object_list_info()
247 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_stolen_list_info()  local
258 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {  in i915_gem_stolen_list_info()
268 	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {  in i915_gem_stolen_list_info()
376 				   struct drm_i915_private *dev_priv)  in print_batch_pool_stats()  argument
384 			    &dev_priv->mm.batch_pool.cache_list,  in print_batch_pool_stats()
406 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_object_info()  local
410 	struct i915_address_space *vm = &dev_priv->gtt.base;  in i915_gem_object_info()
420 		   dev_priv->mm.object_count,  in i915_gem_object_info()
421 		   dev_priv->mm.object_memory);  in i915_gem_object_info()
424 	count_objects(&dev_priv->mm.bound_list, global_list);  in i915_gem_object_info()
439 	list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {  in i915_gem_object_info()
447 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {  in i915_gem_object_info()
469 		   dev_priv->gtt.base.total,  in i915_gem_object_info()
470 		   dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);  in i915_gem_object_info()
473 	print_batch_pool_stats(m, dev_priv);  in i915_gem_object_info()
507 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_gtt_info()  local
517 	list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {  in i915_gem_gtt_info()
541 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_pageflip_info()  local
576 					   dev_priv->next_seqno,  in i915_gem_pageflip_info()
614 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_batch_pool_info()  local
625 			    &dev_priv->mm.batch_pool.cache_list,  in i915_gem_batch_pool_info()
644 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_request_info()  local
654 	for_each_ring(ring, dev_priv, i) {  in i915_gem_request_info()
689 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_seqno_info()  local
696 	intel_runtime_pm_get(dev_priv);  in i915_gem_seqno_info()
698 	for_each_ring(ring, dev_priv, i)  in i915_gem_seqno_info()
701 	intel_runtime_pm_put(dev_priv);  in i915_gem_seqno_info()
712 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_interrupt_info()  local
719 	intel_runtime_pm_get(dev_priv);  in i915_interrupt_info()
733 		for_each_pipe(dev_priv, pipe)  in i915_interrupt_info()
773 		for_each_pipe(dev_priv, pipe) {  in i915_interrupt_info()
774 			if (!intel_display_power_is_enabled(dev_priv,  in i915_interrupt_info()
820 		for_each_pipe(dev_priv, pipe)  in i915_interrupt_info()
856 		for_each_pipe(dev_priv, pipe)  in i915_interrupt_info()
880 	for_each_ring(ring, dev_priv, i) {  in i915_interrupt_info()
888 	intel_runtime_pm_put(dev_priv);  in i915_interrupt_info()
898 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_fence_regs_info()  local
905 	seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);  in i915_gem_fence_regs_info()
906 	seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);  in i915_gem_fence_regs_info()
907 	for (i = 0; i < dev_priv->num_fence_regs; i++) {  in i915_gem_fence_regs_info()
908 		struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;  in i915_gem_fence_regs_info()
911 			   i, dev_priv->fence_regs[i].pin_count);  in i915_gem_fence_regs_info()
927 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_hws_info()  local
932 	ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];  in i915_hws_info()
1038 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_next_seqno_get()  local
1045 	*val = dev_priv->next_seqno;  in i915_next_seqno_get()
1075 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_frequency_info()  local
1078 	intel_runtime_pm_get(dev_priv);  in i915_frequency_info()
1080 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_frequency_info()
1109 		intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);  in i915_frequency_info()
1121 		reqf = intel_gpu_freq(dev_priv, reqf);  in i915_frequency_info()
1140 		cagf = intel_gpu_freq(dev_priv, cagf);  in i915_frequency_info()
1142 		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);  in i915_frequency_info()
1189 			   intel_gpu_freq(dev_priv, max_freq));  in i915_frequency_info()
1194 			   intel_gpu_freq(dev_priv, max_freq));  in i915_frequency_info()
1199 			   intel_gpu_freq(dev_priv, max_freq));  in i915_frequency_info()
1202 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_frequency_info()
1205 			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));  in i915_frequency_info()
1209 		mutex_lock(&dev_priv->rps.hw_lock);  in i915_frequency_info()
1210 		freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);  in i915_frequency_info()
1212 		seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);  in i915_frequency_info()
1215 			   intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));  in i915_frequency_info()
1218 			   intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));  in i915_frequency_info()
1221 			   intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));  in i915_frequency_info()
1225 			   intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));  in i915_frequency_info()
1228 			   intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));  in i915_frequency_info()
1229 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_frequency_info()
1235 	intel_runtime_pm_put(dev_priv);  in i915_frequency_info()
1243 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_hangcheck_info()  local
1254 	intel_runtime_pm_get(dev_priv);  in i915_hangcheck_info()
1256 	for_each_ring(ring, dev_priv, i) {  in i915_hangcheck_info()
1261 	intel_runtime_pm_put(dev_priv);  in i915_hangcheck_info()
1263 	if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {  in i915_hangcheck_info()
1265 			   jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -  in i915_hangcheck_info()
1270 	for_each_ring(ring, dev_priv, i) {  in i915_hangcheck_info()
1290 	struct drm_i915_private *dev_priv = dev->dev_private;  in ironlake_drpc_info()  local
1298 	intel_runtime_pm_get(dev_priv);  in ironlake_drpc_info()
1304 	intel_runtime_pm_put(dev_priv);  in ironlake_drpc_info()
1359 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_forcewake_domains()  local
1363 	spin_lock_irq(&dev_priv->uncore.lock);  in i915_forcewake_domains()
1364 	for_each_fw_domain(fw_domain, dev_priv, i) {  in i915_forcewake_domains()
1369 	spin_unlock_irq(&dev_priv->uncore.lock);  in i915_forcewake_domains()
1378 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_drpc_info()  local
1381 	intel_runtime_pm_get(dev_priv);  in vlv_drpc_info()
1387 	intel_runtime_pm_put(dev_priv);  in vlv_drpc_info()
1418 	struct drm_i915_private *dev_priv = dev->dev_private;  in gen6_drpc_info()  local
1426 	intel_runtime_pm_get(dev_priv);  in gen6_drpc_info()
1428 	spin_lock_irq(&dev_priv->uncore.lock);  in gen6_drpc_info()
1429 	forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;  in gen6_drpc_info()
1430 	spin_unlock_irq(&dev_priv->uncore.lock);  in gen6_drpc_info()
1442 	gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);  in gen6_drpc_info()
1448 	mutex_lock(&dev_priv->rps.hw_lock);  in gen6_drpc_info()
1449 	sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);  in gen6_drpc_info()
1450 	mutex_unlock(&dev_priv->rps.hw_lock);  in gen6_drpc_info()
1452 	intel_runtime_pm_put(dev_priv);  in gen6_drpc_info()
1530 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_fbc_status()  local
1537 	intel_runtime_pm_get(dev_priv);  in i915_fbc_status()
1543 		switch (dev_priv->fbc.no_fbc_reason) {  in i915_fbc_status()
1583 	intel_runtime_pm_put(dev_priv);  in i915_fbc_status()
1591 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_fbc_fc_get()  local
1597 	*val = dev_priv->fbc.false_color;  in i915_fbc_fc_get()
1606 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_fbc_fc_set()  local
1615 	dev_priv->fbc.false_color = val;  in i915_fbc_fc_set()
1633 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ips_status()  local
1640 	intel_runtime_pm_get(dev_priv);  in i915_ips_status()
1654 	intel_runtime_pm_put(dev_priv);  in i915_ips_status()
1663 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_sr_status()  local
1666 	intel_runtime_pm_get(dev_priv);  in i915_sr_status()
1680 	intel_runtime_pm_put(dev_priv);  in i915_sr_status()
1692 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_emon_status()  local
1703 	temp = i915_mch_val(dev_priv);  in i915_emon_status()
1704 	chipset = i915_chipset_val(dev_priv);  in i915_emon_status()
1705 	gfx = i915_gfx_val(dev_priv);  in i915_emon_status()
1720 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_freq_table()  local
1729 	intel_runtime_pm_get(dev_priv);  in i915_ring_freq_table()
1731 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_ring_freq_table()
1733 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_ring_freq_table()
1739 	for (gpu_freq = dev_priv->rps.min_freq_softlimit;  in i915_ring_freq_table()
1740 	     gpu_freq <= dev_priv->rps.max_freq_softlimit;  in i915_ring_freq_table()
1743 		sandybridge_pcode_read(dev_priv,  in i915_ring_freq_table()
1747 			   intel_gpu_freq(dev_priv, gpu_freq),  in i915_ring_freq_table()
1752 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_ring_freq_table()
1755 	intel_runtime_pm_put(dev_priv);  in i915_ring_freq_table()
1763 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_opregion()  local
1764 	struct intel_opregion *opregion = &dev_priv->opregion;  in i915_opregion()
1795 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_gem_framebuffer_info()  local
1797 	ifbdev = dev_priv->fbdev;  in i915_gem_framebuffer_info()
1843 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_context_status()  local
1852 	list_for_each_entry(ctx, &dev_priv->context_list, link) {  in i915_context_status()
1859 		for_each_ring(ring, dev_priv, i) {  in i915_context_status()
1867 			for_each_ring(ring, dev_priv, i) {  in i915_context_status()
1940 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_dump_lrc()  local
1954 	list_for_each_entry(ctx, &dev_priv->context_list, link) {  in i915_dump_lrc()
1955 		for_each_ring(ring, dev_priv, i) {  in i915_dump_lrc()
1971 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_execlists()  local
1991 	intel_runtime_pm_get(dev_priv);  in i915_execlists()
1993 	for_each_ring(ring, dev_priv, ring_id) {  in i915_execlists()
2044 	intel_runtime_pm_put(dev_priv);  in i915_execlists()
2078 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_swizzle_info()  local
2084 	intel_runtime_pm_get(dev_priv);  in i915_swizzle_info()
2087 		   swizzle_string(dev_priv->mm.bit_6_swizzle_x));  in i915_swizzle_info()
2089 		   swizzle_string(dev_priv->mm.bit_6_swizzle_y));  in i915_swizzle_info()
2119 	if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)  in i915_swizzle_info()
2122 	intel_runtime_pm_put(dev_priv);  in i915_swizzle_info()
2151 	struct drm_i915_private *dev_priv = dev->dev_private;  in gen8_ppgtt_info()  local
2153 	struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;  in gen8_ppgtt_info()
2161 	for_each_ring(ring, dev_priv, unused) {  in gen8_ppgtt_info()
2175 	struct drm_i915_private *dev_priv = dev->dev_private;  in gen6_ppgtt_info()  local
2183 	for_each_ring(ring, dev_priv, i) {  in gen6_ppgtt_info()
2191 	if (dev_priv->mm.aliasing_ppgtt) {  in gen6_ppgtt_info()
2192 		struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;  in gen6_ppgtt_info()
2214 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ppgtt_info()  local
2219 	intel_runtime_pm_get(dev_priv);  in i915_ppgtt_info()
2226 	intel_runtime_pm_put(dev_priv);  in i915_ppgtt_info()
2236 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_llc()  local
2240 	seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);  in i915_llc()
2249 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_edp_psr_status()  local
2260 	intel_runtime_pm_get(dev_priv);  in i915_edp_psr_status()
2262 	mutex_lock(&dev_priv->psr.lock);  in i915_edp_psr_status()
2263 	seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));  in i915_edp_psr_status()
2264 	seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));  in i915_edp_psr_status()
2265 	seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));  in i915_edp_psr_status()
2266 	seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));  in i915_edp_psr_status()
2268 		   dev_priv->psr.busy_frontbuffer_bits);  in i915_edp_psr_status()
2270 		   yesno(work_busy(&dev_priv->psr.work.work)));  in i915_edp_psr_status()
2275 		for_each_pipe(dev_priv, pipe) {  in i915_edp_psr_status()
2286 		for_each_pipe(dev_priv, pipe) {  in i915_edp_psr_status()
2294 		   yesno((bool)dev_priv->psr.link_standby));  in i915_edp_psr_status()
2303 	mutex_unlock(&dev_priv->psr.lock);  in i915_edp_psr_status()
2305 	intel_runtime_pm_put(dev_priv);  in i915_edp_psr_status()
2353 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_energy_uJ()  local
2360 	intel_runtime_pm_get(dev_priv);  in i915_energy_uJ()
2368 	intel_runtime_pm_put(dev_priv);  in i915_energy_uJ()
2379 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_pc8_status()  local
2386 	seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));  in i915_pc8_status()
2388 		   yesno(!intel_irqs_enabled(dev_priv)));  in i915_pc8_status()
2464 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_power_domain_info()  local
2465 	struct i915_power_domains *power_domains = &dev_priv->power_domains;  in i915_power_domain_info()
2633 	struct drm_i915_private *dev_priv = dev->dev_private;  in cursor_active()  local
2646 	struct drm_i915_private *dev_priv = dev->dev_private;  in cursor_position()  local
2666 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_display_info()  local
2670 	intel_runtime_pm_get(dev_priv);  in i915_display_info()
2705 	intel_runtime_pm_put(dev_priv);  in i915_display_info()
2714 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_semaphore_status()  local
2727 	intel_runtime_pm_get(dev_priv);  in i915_semaphore_status()
2733 		page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);  in i915_semaphore_status()
2736 		for_each_ring(ring, dev_priv, i) {  in i915_semaphore_status()
2761 		for_each_ring(ring, dev_priv, i)  in i915_semaphore_status()
2769 	for_each_ring(ring, dev_priv, i) {  in i915_semaphore_status()
2777 	intel_runtime_pm_put(dev_priv);  in i915_semaphore_status()
2786 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_shared_dplls_info()  local
2790 	for (i = 0; i < dev_priv->num_shared_dpll; i++) {  in i915_shared_dplls_info()
2791 		struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];  in i915_shared_dplls_info()
2815 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_wa_registers()  local
2821 	intel_runtime_pm_get(dev_priv);  in i915_wa_registers()
2823 	seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);  in i915_wa_registers()
2824 	for (i = 0; i < dev_priv->workarounds.count; ++i) {  in i915_wa_registers()
2828 		addr = dev_priv->workarounds.reg[i].addr;  in i915_wa_registers()
2829 		mask = dev_priv->workarounds.reg[i].mask;  in i915_wa_registers()
2830 		value = dev_priv->workarounds.reg[i].value;  in i915_wa_registers()
2837 	intel_runtime_pm_put(dev_priv);  in i915_wa_registers()
2847 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ddb_info()  local
2858 	ddb = &dev_priv->wm.skl_hw.ddb;  in i915_ddb_info()
2862 	for_each_pipe(dev_priv, pipe) {  in i915_ddb_info()
2865 		for_each_plane(dev_priv, pipe, plane) {  in i915_ddb_info()
2886 	struct drm_i915_private *dev_priv = dev->dev_private;  in drrs_status_per_crtc()  local
2887 	struct i915_drrs *drrs = &dev_priv->drrs;  in drrs_status_per_crtc()
2912 	if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)  in drrs_status_per_crtc()
2914 	else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)  in drrs_status_per_crtc()
2916 	else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)  in drrs_status_per_crtc()
3022 	struct drm_i915_private *dev_priv = info->dev->dev_private;  in i915_pipe_crc_open()  local
3023 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];  in i915_pipe_crc_open()
3046 	struct drm_i915_private *dev_priv = info->dev->dev_private;  in i915_pipe_crc_release()  local
3047 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];  in i915_pipe_crc_release()
3074 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_pipe_crc_read()  local
3075 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];  in i915_pipe_crc_read()
3207 	struct drm_i915_private *dev_priv = dev->dev_private;  in display_crc_ctl_show()  local
3212 			   pipe_crc_source_name(dev_priv->pipe_crc[i].source));  in display_crc_ctl_show()
3301 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_pipe_crc_ctl_reg()  local
3372 	struct drm_i915_private *dev_priv = dev->dev_private;  in i9xx_pipe_crc_ctl_reg()  local
3446 	struct drm_i915_private *dev_priv = dev->dev_private;  in vlv_undo_pipe_scramble_reset()  local
3471 	struct drm_i915_private *dev_priv = dev->dev_private;  in g4x_undo_pipe_scramble_reset()  local
3514 	struct drm_i915_private *dev_priv = dev->dev_private;  in hsw_trans_edp_pipe_A_crc_wa()  local
3516 		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);  in hsw_trans_edp_pipe_A_crc_wa()
3529 		intel_display_power_get(dev_priv,  in hsw_trans_edp_pipe_A_crc_wa()
3532 		dev_priv->display.crtc_disable(&crtc->base);  in hsw_trans_edp_pipe_A_crc_wa()
3533 		dev_priv->display.crtc_enable(&crtc->base);  in hsw_trans_edp_pipe_A_crc_wa()
3540 	struct drm_i915_private *dev_priv = dev->dev_private;  in hsw_undo_trans_edp_pipe_A_crc_wa()  local
3542 		to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);  in hsw_undo_trans_edp_pipe_A_crc_wa()
3554 		dev_priv->display.crtc_disable(&crtc->base);  in hsw_undo_trans_edp_pipe_A_crc_wa()
3555 		dev_priv->display.crtc_enable(&crtc->base);  in hsw_undo_trans_edp_pipe_A_crc_wa()
3557 		intel_display_power_put(dev_priv,  in hsw_undo_trans_edp_pipe_A_crc_wa()
3597 	struct drm_i915_private *dev_priv = dev->dev_private;  in pipe_crc_set_source()  local
3598 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];  in pipe_crc_set_source()
3611 	if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {  in pipe_crc_set_source()
3668 			to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);  in pipe_crc_set_source()
3902 	struct drm_i915_private *dev_priv = dev->dev_private;  in pri_wm_latency_show()  local
3906 		latencies = dev_priv->wm.skl_latency;  in pri_wm_latency_show()
3918 	struct drm_i915_private *dev_priv = dev->dev_private;  in spr_wm_latency_show()  local
3922 		latencies = dev_priv->wm.skl_latency;  in spr_wm_latency_show()
3934 	struct drm_i915_private *dev_priv = dev->dev_private;  in cur_wm_latency_show()  local
3938 		latencies = dev_priv->wm.skl_latency;  in cur_wm_latency_show()
4018 	struct drm_i915_private *dev_priv = dev->dev_private;  in pri_wm_latency_write()  local
4022 		latencies = dev_priv->wm.skl_latency;  in pri_wm_latency_write()
4034 	struct drm_i915_private *dev_priv = dev->dev_private;  in spr_wm_latency_write()  local
4038 		latencies = dev_priv->wm.skl_latency;  in spr_wm_latency_write()
4050 	struct drm_i915_private *dev_priv = dev->dev_private;  in cur_wm_latency_write()  local
4054 		latencies = dev_priv->wm.skl_latency;  in cur_wm_latency_write()
4092 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_wedged_get()  local
4094 	*val = atomic_read(&dev_priv->gpu_error.reset_counter);  in i915_wedged_get()
4103 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_wedged_set()  local
4113 	if (i915_reset_in_progress(&dev_priv->gpu_error))  in i915_wedged_set()
4116 	intel_runtime_pm_get(dev_priv);  in i915_wedged_set()
4121 	intel_runtime_pm_put(dev_priv);  in i915_wedged_set()
4134 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_stop_get()  local
4136 	*val = dev_priv->gpu_error.stop_rings;  in i915_ring_stop_get()
4145 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_stop_set()  local
4154 	dev_priv->gpu_error.stop_rings = val;  in i915_ring_stop_set()
4168 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_missed_irq_get()  local
4170 	*val = dev_priv->gpu_error.missed_irq_rings;  in i915_ring_missed_irq_get()
4178 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_missed_irq_set()  local
4185 	dev_priv->gpu_error.missed_irq_rings = val;  in i915_ring_missed_irq_set()
4199 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_test_irq_get()  local
4201 	*val = dev_priv->gpu_error.test_irq_rings;  in i915_ring_test_irq_get()
4210 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_ring_test_irq_set()  local
4220 	dev_priv->gpu_error.test_irq_rings = val;  in i915_ring_test_irq_set()
4250 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_drop_caches_set()  local
4271 		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);  in i915_drop_caches_set()
4274 		i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);  in i915_drop_caches_set()
4290 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_max_freq_get()  local
4296 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_max_freq_get()
4298 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_max_freq_get()
4302 	*val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);  in i915_max_freq_get()
4303 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_get()
4312 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_max_freq_set()  local
4319 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_max_freq_set()
4323 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4330 	val = intel_freq_opcode(dev_priv, val);  in i915_max_freq_set()
4332 	hw_max = dev_priv->rps.max_freq;  in i915_max_freq_set()
4333 	hw_min = dev_priv->rps.min_freq;  in i915_max_freq_set()
4335 	if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {  in i915_max_freq_set()
4336 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4340 	dev_priv->rps.max_freq_softlimit = val;  in i915_max_freq_set()
4344 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_max_freq_set()
4357 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_min_freq_get()  local
4363 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_min_freq_get()
4365 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_min_freq_get()
4369 	*val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);  in i915_min_freq_get()
4370 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_get()
4379 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_min_freq_set()  local
4386 	flush_delayed_work(&dev_priv->rps.delayed_resume_work);  in i915_min_freq_set()
4390 	ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4397 	val = intel_freq_opcode(dev_priv, val);  in i915_min_freq_set()
4399 	hw_max = dev_priv->rps.max_freq;  in i915_min_freq_set()
4400 	hw_min = dev_priv->rps.min_freq;  in i915_min_freq_set()
4402 	if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {  in i915_min_freq_set()
4403 		mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4407 	dev_priv->rps.min_freq_softlimit = val;  in i915_min_freq_set()
4411 	mutex_unlock(&dev_priv->rps.hw_lock);  in i915_min_freq_set()
4424 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_cache_sharing_get()  local
4434 	intel_runtime_pm_get(dev_priv);  in i915_cache_sharing_get()
4438 	intel_runtime_pm_put(dev_priv);  in i915_cache_sharing_get()
4439 	mutex_unlock(&dev_priv->dev->struct_mutex);  in i915_cache_sharing_get()
4450 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_cache_sharing_set()  local
4459 	intel_runtime_pm_get(dev_priv);  in i915_cache_sharing_set()
4468 	intel_runtime_pm_put(dev_priv);  in i915_cache_sharing_set()
4480 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_sseu_status()  local
4585 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_forcewake_open()  local
4590 	intel_runtime_pm_get(dev_priv);  in i915_forcewake_open()
4591 	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);  in i915_forcewake_open()
4599 	struct drm_i915_private *dev_priv = dev->dev_private;  in i915_forcewake_release()  local
4604 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);  in i915_forcewake_release()
4605 	intel_runtime_pm_put(dev_priv);  in i915_forcewake_release()
4723 	struct drm_i915_private *dev_priv = dev->dev_private;  in intel_display_crc_init()  local
4726 	for_each_pipe(dev_priv, pipe) {  in intel_display_crc_init()
4727 		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];  in intel_display_crc_init()