338 	uint32_t saveVCLK_DIVISOR_VGA0;
339 	uint32_t saveVCLK_DIVISOR_VGA1;
340 	uint32_t saveVCLK_POST_DIV;
341 	uint32_t saveVGACNTRL;
342 	uint32_t saveADPA;
343 	uint32_t saveLVDS;
344 	uint32_t saveDVOA;
345 	uint32_t saveDVOB;
346 	uint32_t saveDVOC;
347 	uint32_t savePP_ON;
348 	uint32_t savePP_OFF;
349 	uint32_t savePP_CONTROL;
350 	uint32_t savePP_CYCLE;
351 	uint32_t savePFIT_CONTROL;
352 	uint32_t saveCLOCKGATING;
353 	uint32_t saveDSPARB;
354 	uint32_t savePFIT_AUTO_RATIOS;
355 	uint32_t savePFIT_PGM_RATIOS;
356 	uint32_t savePP_ON_DELAYS;
357 	uint32_t savePP_OFF_DELAYS;
358 	uint32_t savePP_DIVISOR;
359 	uint32_t saveBCLRPAT_A;
360 	uint32_t saveBCLRPAT_B;
361 	uint32_t savePERF_MODE;
362 	uint32_t saveDSPFW1;
363 	uint32_t saveDSPFW2;
364 	uint32_t saveDSPFW3;
365 	uint32_t saveDSPFW4;
366 	uint32_t saveDSPFW5;
367 	uint32_t saveDSPFW6;
368 	uint32_t saveCHICKENBIT;
369 	uint32_t saveDSPACURSOR_CTRL;
370 	uint32_t saveDSPBCURSOR_CTRL;
371 	uint32_t saveDSPACURSOR_BASE;
372 	uint32_t saveDSPBCURSOR_BASE;
373 	uint32_t saveDSPACURSOR_POS;
374 	uint32_t saveDSPBCURSOR_POS;
375 	uint32_t saveOV_OVADD;
376 	uint32_t saveOV_OGAMC0;
377 	uint32_t saveOV_OGAMC1;
378 	uint32_t saveOV_OGAMC2;
379 	uint32_t saveOV_OGAMC3;
380 	uint32_t saveOV_OGAMC4;
381 	uint32_t saveOV_OGAMC5;
382 	uint32_t saveOVC_OVADD;
383 	uint32_t saveOVC_OGAMC0;
384 	uint32_t saveOVC_OGAMC1;
385 	uint32_t saveOVC_OGAMC2;
386 	uint32_t saveOVC_OGAMC3;
387 	uint32_t saveOVC_OGAMC4;
388 	uint32_t saveOVC_OGAMC5;
391 	uint32_t saveHISTOGRAM_INT_CONTROL_REG;
392 	uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
393 	uint32_t savePWM_CONTROL_LOGIC;
397 	uint32_t saveMIPI;
398 	uint32_t saveMIPI_C;
400 	uint32_t savePFIT_CONTROL;
401 	uint32_t savePFIT_PGM_RATIOS;
402 	uint32_t saveHDMIPHYMISCCTL;
403 	uint32_t saveHDMIB_CONTROL;
407 	uint32_t saveDSPCLK_GATE_D;
408 	uint32_t saveRAMCLK_GATE_D;
409 	uint32_t saveDSPARB;
410 	uint32_t saveDSPFW[6];
411 	uint32_t saveADPA;
412 	uint32_t savePP_CONTROL;
413 	uint32_t savePFIT_PGM_RATIOS;
414 	uint32_t saveLVDS;
415 	uint32_t savePFIT_CONTROL;
416 	uint32_t savePP_ON_DELAYS;
417 	uint32_t savePP_OFF_DELAYS;
418 	uint32_t savePP_CYCLE;
419 	uint32_t saveVGACNTRL;
420 	uint32_t saveIER;
421 	uint32_t saveIMR;
427 	uint32_t saveBSM;
428 	uint32_t saveVBT;
434 	uint32_t saveBLC_PWM_CTL2;
435 	uint32_t saveBLC_PWM_CTL;
458 	uint32_t stolen_base;
476 	uint32_t gatt_free_offset;
479 	uint32_t vdc_irq_mask;
480 	uint32_t pipestat[PSB_NUM_PIPE];
495 	uint32_t num_pipe;
498 	uint32_t ospm_base;
542 	uint32_t iLVDS_enable;
558 	uint32_t msi_addr;
559 	uint32_t msi_data;
571 	uint32_t apm_reg;
582 	uint32_t blc_adj1;
583 	uint32_t blc_adj2;
750 			uint32_t handle, uint64_t *offset);
789 	uint32_t ret_val = 0;  in MRST_MSG_READ32()
807 	uint32_t ret_val = 0;  in MDFLD_MSG_READ32()
823 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)  in REGISTER_READ()
829 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)  in REGISTER_READ_AUX()
839 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,  in REGISTER_READ_WITH_AUX()
840 					      uint32_t reg, int aux)  in REGISTER_READ_WITH_AUX()
842 	uint32_t val;  in REGISTER_READ_WITH_AUX()
854 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,  in REGISTER_WRITE()
855 				  uint32_t val)  in REGISTER_WRITE()
861 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,  in REGISTER_WRITE_AUX()
862 				      uint32_t val)  in REGISTER_WRITE_AUX()
871 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,  in REGISTER_WRITE_WITH_AUX()
872 				      uint32_t val, int aux)  in REGISTER_WRITE_WITH_AUX()
883 					uint32_t reg, uint32_t val)  in REGISTER_WRITE16()
892 				       uint32_t reg, uint32_t val)  in REGISTER_WRITE8()