51 void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe)  in mdfldWaitForPipeDisable()  argument
54 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfldWaitForPipeDisable()
57 	switch (pipe) {  in mdfldWaitForPipeDisable()
79 void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe)  in mdfldWaitForPipeEnable()  argument
82 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfldWaitForPipeEnable()
85 	switch (pipe) {  in mdfldWaitForPipeEnable()
170 	int pipe = gma_crtc->pipe;  in mdfld__intel_pipe_set_base()  local
171 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld__intel_pipe_set_base()
178 	dev_dbg(dev->dev, "pipe = 0x%x.\n", pipe);  in mdfld__intel_pipe_set_base()
190 	if (pipe > 2) {  in mdfld__intel_pipe_set_base()
238 void mdfld_disable_crtc(struct drm_device *dev, int pipe)  in mdfld_disable_crtc()  argument
241 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld_disable_crtc()
244 	dev_dbg(dev->dev, "pipe = %d\n", pipe);  in mdfld_disable_crtc()
247 	if (pipe != 1)  in mdfld_disable_crtc()
248 		mdfld_dsi_gen_fifo_ready(dev, MIPI_GEN_FIFO_STAT_REG(pipe),  in mdfld_disable_crtc()
272 		mdfldWaitForPipeDisable(dev, pipe);  in mdfld_disable_crtc()
277 		if ((pipe != 1 &&  in mdfld_disable_crtc()
279 				& PIPEACONF_ENABLE)) || pipe == 1) {  in mdfld_disable_crtc()
309 	int pipe = gma_crtc->pipe;  in mdfld_crtc_dpms()  local
310 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld_crtc_dpms()
311 	u32 pipeconf = dev_priv->pipeconf[pipe];  in mdfld_crtc_dpms()
315 	dev_dbg(dev->dev, "mode = %d, pipe = %d\n", mode, pipe);  in mdfld_crtc_dpms()
356 			while ((pipe != 2) && (timeout < 20000) &&  in mdfld_crtc_dpms()
378 			mdfldWaitForPipeEnable(dev, pipe);  in mdfld_crtc_dpms()
383 		if (pipe == 0 || pipe == 2) {  in mdfld_crtc_dpms()
402 				REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 0);  in mdfld_crtc_dpms()
406 				REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 1);  in mdfld_crtc_dpms()
431 		if (pipe != 1)  in mdfld_crtc_dpms()
433 				MIPI_GEN_FIFO_STAT_REG(pipe),  in mdfld_crtc_dpms()
458 			mdfldWaitForPipeDisable(dev, pipe);  in mdfld_crtc_dpms()
463 			if ((pipe != 1 && !((REG_READ(PIPEACONF)  in mdfld_crtc_dpms()
465 					|| pipe == 1) {  in mdfld_crtc_dpms()
674 	int pipe = gma_crtc->pipe;  in mdfld_crtc_mode_set()  local
675 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld_crtc_mode_set()
691 	dev_dbg(dev->dev, "pipe = 0x%x\n", pipe);  in mdfld_crtc_mode_set()
694 	if (pipe == 1) {  in mdfld_crtc_mode_set()
769 	if (psb_intel_panel_fitter_pipe(dev) == pipe)  in mdfld_crtc_mode_set()
775 	if (pipe == 1) {  in mdfld_crtc_mode_set()
858 	dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */  in mdfld_crtc_mode_set()
861 	dev_priv->dspcntr[pipe] = REG_READ(map->cntr);  in mdfld_crtc_mode_set()
862 	dev_priv->dspcntr[pipe] |= pipe << DISPPLANE_SEL_PIPE_POS;  in mdfld_crtc_mode_set()
863 	dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE;  in mdfld_crtc_mode_set()
1013 	REG_WRITE(map->conf, dev_priv->pipeconf[pipe]);  in mdfld_crtc_mode_set()
1017 	REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);  in mdfld_crtc_mode_set()