Lines Matching refs:map
54 const struct psb_offset *map = &dev_priv->regmap[pipe]; in mdfldWaitForPipeDisable() local
73 temp = REG_READ(map->conf); in mdfldWaitForPipeDisable()
82 const struct psb_offset *map = &dev_priv->regmap[pipe]; in mdfldWaitForPipeEnable() local
101 temp = REG_READ(map->conf); in mdfldWaitForPipeEnable()
171 const struct psb_offset *map = &dev_priv->regmap[pipe]; in mdfld__intel_pipe_set_base() local
201 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); in mdfld__intel_pipe_set_base()
202 dspcntr = REG_READ(map->cntr); in mdfld__intel_pipe_set_base()
220 REG_WRITE(map->cntr, dspcntr); in mdfld__intel_pipe_set_base()
224 REG_WRITE(map->linoff, offset); in mdfld__intel_pipe_set_base()
225 REG_READ(map->linoff); in mdfld__intel_pipe_set_base()
226 REG_WRITE(map->surf, start); in mdfld__intel_pipe_set_base()
227 REG_READ(map->surf); in mdfld__intel_pipe_set_base()
241 const struct psb_offset *map = &dev_priv->regmap[pipe]; in mdfld_disable_crtc() local
252 temp = REG_READ(map->cntr); in mdfld_disable_crtc()
254 REG_WRITE(map->cntr, in mdfld_disable_crtc()
257 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
258 REG_READ(map->base); in mdfld_disable_crtc()
264 temp = REG_READ(map->conf); in mdfld_disable_crtc()
268 REG_WRITE(map->conf, temp); in mdfld_disable_crtc()
269 REG_READ(map->conf); in mdfld_disable_crtc()
275 temp = REG_READ(map->dpll); in mdfld_disable_crtc()
281 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
282 REG_READ(map->dpll); in mdfld_disable_crtc()
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
310 const struct psb_offset *map = &dev_priv->regmap[pipe]; in mdfld_crtc_dpms() local
331 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
338 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
343 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
344 REG_READ(map->dpll); in mdfld_crtc_dpms()
348 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
349 REG_READ(map->dpll); in mdfld_crtc_dpms()
357 !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) { in mdfld_crtc_dpms()
364 temp = REG_READ(map->cntr); in mdfld_crtc_dpms()
366 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
369 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
373 temp = REG_READ(map->conf); in mdfld_crtc_dpms()
375 REG_WRITE(map->conf, pipeconf); in mdfld_crtc_dpms()
384 REG_WRITE(map->status, REG_READ(map->status)); in mdfld_crtc_dpms()
386 if (PIPE_VBLANK_STATUS & REG_READ(map->status)) in mdfld_crtc_dpms()
391 temp = REG_READ(map->cntr); in mdfld_crtc_dpms()
392 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
394 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
398 temp = REG_READ(map->conf); in mdfld_crtc_dpms()
400 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
407 temp = REG_READ(map->cntr); in mdfld_crtc_dpms()
408 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
410 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
414 temp = REG_READ(map->conf); in mdfld_crtc_dpms()
416 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
440 temp = REG_READ(map->cntr); in mdfld_crtc_dpms()
442 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
445 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
446 REG_READ(map->base); in mdfld_crtc_dpms()
450 temp = REG_READ(map->conf); in mdfld_crtc_dpms()
454 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
455 REG_READ(map->conf); in mdfld_crtc_dpms()
461 temp = REG_READ(map->dpll); in mdfld_crtc_dpms()
467 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
468 REG_READ(map->dpll); in mdfld_crtc_dpms()
675 const struct psb_offset *map = &dev_priv->regmap[pipe]; in mdfld_crtc_mode_set() local
787 REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16) in mdfld_crtc_mode_set()
790 REG_WRITE(map->src, ((mode->crtc_hdisplay - 1) << 16) in mdfld_crtc_mode_set()
793 REG_WRITE(map->size, in mdfld_crtc_mode_set()
796 REG_WRITE(map->src, in mdfld_crtc_mode_set()
801 REG_WRITE(map->pos, 0); in mdfld_crtc_mode_set()
819 REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) | in mdfld_crtc_mode_set()
821 REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) | in mdfld_crtc_mode_set()
823 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - in mdfld_crtc_mode_set()
826 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - in mdfld_crtc_mode_set()
829 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - in mdfld_crtc_mode_set()
832 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - in mdfld_crtc_mode_set()
836 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in mdfld_crtc_mode_set()
838 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in mdfld_crtc_mode_set()
840 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in mdfld_crtc_mode_set()
842 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in mdfld_crtc_mode_set()
844 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in mdfld_crtc_mode_set()
846 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in mdfld_crtc_mode_set()
861 dev_priv->dspcntr[pipe] = REG_READ(map->cntr); in mdfld_crtc_mode_set()
928 dpll = REG_READ(map->dpll); in mdfld_crtc_mode_set()
932 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
933 REG_READ(map->dpll); in mdfld_crtc_mode_set()
940 REG_WRITE(map->fp0, 0); in mdfld_crtc_mode_set()
942 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
951 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
992 REG_WRITE(map->fp0, fp); in mdfld_crtc_mode_set()
993 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
998 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
999 REG_READ(map->dpll); in mdfld_crtc_mode_set()
1003 !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) { in mdfld_crtc_mode_set()
1013 REG_WRITE(map->conf, dev_priv->pipeconf[pipe]); in mdfld_crtc_mode_set()
1014 REG_READ(map->conf); in mdfld_crtc_mode_set()
1017 REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); in mdfld_crtc_mode_set()