Lines Matching refs:dspcntr
131 u32 dspcntr; in mdfld__intel_plane_set_alpha() local
133 dspcntr = REG_READ(dspcntr_reg); in mdfld__intel_plane_set_alpha()
136 dspcntr &= ~DISPPLANE_32BPP_NO_ALPHA; in mdfld__intel_plane_set_alpha()
137 dspcntr |= DISPPLANE_32BPP; in mdfld__intel_plane_set_alpha()
139 dspcntr &= ~DISPPLANE_32BPP; in mdfld__intel_plane_set_alpha()
140 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; in mdfld__intel_plane_set_alpha()
143 REG_WRITE(dspcntr_reg, dspcntr); in mdfld__intel_plane_set_alpha()
173 u32 dspcntr; in mdfld__intel_pipe_set_base() local
202 dspcntr = REG_READ(map->cntr); in mdfld__intel_pipe_set_base()
203 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; in mdfld__intel_pipe_set_base()
207 dspcntr |= DISPPLANE_8BPP; in mdfld__intel_pipe_set_base()
211 dspcntr |= DISPPLANE_15_16BPP; in mdfld__intel_pipe_set_base()
213 dspcntr |= DISPPLANE_16BPP; in mdfld__intel_pipe_set_base()
217 dspcntr |= DISPPLANE_32BPP_NO_ALPHA; in mdfld__intel_pipe_set_base()
220 REG_WRITE(map->cntr, dspcntr); in mdfld__intel_pipe_set_base()
861 dev_priv->dspcntr[pipe] = REG_READ(map->cntr); in mdfld_crtc_mode_set()
862 dev_priv->dspcntr[pipe] |= pipe << DISPPLANE_SEL_PIPE_POS; in mdfld_crtc_mode_set()
863 dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE; in mdfld_crtc_mode_set()
1017 REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); in mdfld_crtc_mode_set()