53 	struct drm_psb_private *dev_priv = dev->dev_private;  in mdfldWaitForPipeDisable()  local
54 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfldWaitForPipeDisable()
81 	struct drm_psb_private *dev_priv = dev->dev_private;  in mdfldWaitForPipeEnable()  local
82 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfldWaitForPipeEnable()
167 	struct drm_psb_private *dev_priv = dev->dev_private;  in mdfld__intel_pipe_set_base()  local
171 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld__intel_pipe_set_base()
240 	struct drm_psb_private *dev_priv = dev->dev_private;  in mdfld_disable_crtc()  local
241 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld_disable_crtc()
307 	struct drm_psb_private *dev_priv = dev->dev_private;  in mdfld_crtc_dpms()  local
310 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld_crtc_dpms()
311 	u32 pipeconf = dev_priv->pipeconf[pipe];  in mdfld_crtc_dpms()
593 	struct drm_psb_private *dev_priv = dev->dev_private;  in mdfld_limit()  local
602 				(dev_priv->core_freq == 166))  in mdfld_limit()
605 			 (dev_priv->core_freq == 100 ||  in mdfld_limit()
606 				dev_priv->core_freq == 200))  in mdfld_limit()
614 				(dev_priv->core_freq == 166))  in mdfld_limit()
617 				 (dev_priv->core_freq == 100 ||  in mdfld_limit()
618 				 dev_priv->core_freq == 200))  in mdfld_limit()
673 	struct drm_psb_private *dev_priv = dev->dev_private;  in mdfld_crtc_mode_set()  local
675 	const struct psb_offset *map = &dev_priv->regmap[pipe];  in mdfld_crtc_mode_set()
858 	dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */  in mdfld_crtc_mode_set()
861 	dev_priv->dspcntr[pipe] = REG_READ(map->cntr);  in mdfld_crtc_mode_set()
862 	dev_priv->dspcntr[pipe] |= pipe << DISPPLANE_SEL_PIPE_POS;  in mdfld_crtc_mode_set()
863 	dev_priv->dspcntr[pipe] |= DISPLAY_PLANE_ENABLE;  in mdfld_crtc_mode_set()
885 					dev_priv->core_freq == 166) {  in mdfld_crtc_mode_set()
893 					(dev_priv->core_freq == 100 ||  in mdfld_crtc_mode_set()
894 					dev_priv->core_freq == 200)) {  in mdfld_crtc_mode_set()
903 			clk_byte = dev_priv->bpp / 8;  in mdfld_crtc_mode_set()
905 			clk_byte = dev_priv->bpp2 / 8;  in mdfld_crtc_mode_set()
1013 	REG_WRITE(map->conf, dev_priv->pipeconf[pipe]);  in mdfld_crtc_mode_set()
1017 	REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]);  in mdfld_crtc_mode_set()