Lines Matching refs:pipe
35 int pipe);
37 static void mdfld_wait_for_HS_DATA_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_DATA_FIFO() argument
39 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_DATA_FIFO()
55 static void mdfld_wait_for_HS_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_HS_CTRL_FIFO() argument
57 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_HS_CTRL_FIFO()
72 static void mdfld_wait_for_DPI_CTRL_FIFO(struct drm_device *dev, u32 pipe) in mdfld_wait_for_DPI_CTRL_FIFO() argument
74 u32 gen_fifo_stat_reg = MIPI_GEN_FIFO_STAT_REG(pipe); in mdfld_wait_for_DPI_CTRL_FIFO()
90 static void mdfld_wait_for_SPL_PKG_SENT(struct drm_device *dev, u32 pipe) in mdfld_wait_for_SPL_PKG_SENT() argument
92 u32 intr_stat_reg = MIPI_INTR_STAT_REG(pipe); in mdfld_wait_for_SPL_PKG_SENT()
111 int pipe) in dsi_set_device_ready_state() argument
113 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0); in dsi_set_device_ready_state()
117 int state, int pipe) in dsi_set_pipe_plane_enable_state() argument
123 u32 dspcntr = dev_priv->dspcntr[pipe]; in dsi_set_pipe_plane_enable_state()
126 if (pipe) { in dsi_set_pipe_plane_enable_state()
143 u32 dspbase_reg = pipe ? MDFLD_DSPCBASE : MRST_DSPABASE; in dsi_set_pipe_plane_enable_state()
146 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); in dsi_set_pipe_plane_enable_state()
147 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
150 REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16); in dsi_set_pipe_plane_enable_state()
151 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
167 if (REG_BIT_WAIT(MIPI_GEN_FIFO_STAT_REG(pipe), 1, 28)) in dsi_set_pipe_plane_enable_state()
174 int pipe) in mdfld_dsi_configure_down() argument
183 if (!dev_priv->dpi_panel_on[pipe]) { in mdfld_dsi_configure_down()
189 dsi_set_pipe_plane_enable_state(dev, 0, pipe); in mdfld_dsi_configure_down()
190 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_configure_down()
191 dsi_set_device_ready_state(dev, 0, pipe); in mdfld_dsi_configure_down()
195 int pipe) in mdfld_dsi_configure_up() argument
204 if (dev_priv->dpi_panel_on[pipe]) { in mdfld_dsi_configure_up()
210 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_configure_up()
211 dsi_set_device_ready_state(dev, 0, pipe); in mdfld_dsi_configure_up()
213 dsi_set_device_ready_state(dev, 1, pipe); in mdfld_dsi_configure_up()
216 mdfld_dsi_dpi_turn_on(dpi_output, pipe); /* Send turn on command */ in mdfld_dsi_configure_up()
217 dsi_set_pipe_plane_enable_state(dev, 1, pipe); in mdfld_dsi_configure_up()
229 static void mdfld_dsi_tpo_ic_init(struct mdfld_dsi_config *dsi_config, u32 pipe) in mdfld_dsi_tpo_ic_init() argument
233 u32 gen_data_reg = MIPI_HS_GEN_DATA_REG(pipe); in mdfld_dsi_tpo_ic_init()
234 u32 gen_ctrl_reg = MIPI_HS_GEN_CTRL_REG(pipe); in mdfld_dsi_tpo_ic_init()
242 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
244 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
248 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
250 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
254 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
256 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
260 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
262 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
266 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
268 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
270 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
274 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
276 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
280 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
282 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
284 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
286 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
290 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
292 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
294 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
296 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
298 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
302 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
304 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
306 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
310 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
312 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
316 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
318 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
320 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
322 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
324 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
326 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
330 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
332 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
334 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
336 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
340 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
342 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
344 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
346 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
350 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
352 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
354 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
356 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
358 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
360 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
362 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
364 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
366 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
368 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
370 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
372 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
374 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
376 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
380 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
382 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
384 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
386 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
388 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
390 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
392 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
394 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
396 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
398 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
400 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
402 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
404 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
406 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
410 mdfld_wait_for_HS_DATA_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
412 mdfld_wait_for_HS_CTRL_FIFO(dev, pipe); in mdfld_dsi_tpo_ic_init()
467 int pipe) in mdfld_dsi_dpi_controller_init() argument
476 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); in mdfld_dsi_dpi_controller_init()
479 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); in mdfld_dsi_dpi_controller_init()
482 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); in mdfld_dsi_dpi_controller_init()
502 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); in mdfld_dsi_dpi_controller_init()
504 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
507 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
511 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
515 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), in mdfld_dsi_dpi_controller_init()
518 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), in mdfld_dsi_dpi_controller_init()
525 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
527 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
529 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
531 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
533 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
535 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
537 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
540 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46); in mdfld_dsi_dpi_controller_init()
543 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0); in mdfld_dsi_dpi_controller_init()
547 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); in mdfld_dsi_dpi_controller_init()
549 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); in mdfld_dsi_dpi_controller_init()
551 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); in mdfld_dsi_dpi_controller_init()
554 if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_controller_init()
555 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); in mdfld_dsi_dpi_controller_init()
557 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408); in mdfld_dsi_dpi_controller_init()
559 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); in mdfld_dsi_dpi_controller_init()
561 if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_controller_init()
565 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0); in mdfld_dsi_dpi_controller_init()
568 void mdfld_dsi_dpi_turn_on(struct mdfld_dsi_dpi_output *output, int pipe) in mdfld_dsi_dpi_turn_on() argument
573 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
574 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_turn_on()
578 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_TURN_ON); in mdfld_dsi_dpi_turn_on()
581 mdfld_wait_for_SPL_PKG_SENT(dev, pipe); in mdfld_dsi_dpi_turn_on()
583 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
584 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_turn_on()
598 int pipe) in mdfld_dsi_dpi_shut_down() argument
609 mdfld_wait_for_DPI_CTRL_FIFO(dev, pipe); in mdfld_dsi_dpi_shut_down()
612 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_shut_down()
613 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_shut_down()
616 if (REG_READ(MIPI_DPI_CONTROL_REG(pipe)) == DSI_DPI_CTRL_HS_SHUTDOWN) in mdfld_dsi_dpi_shut_down()
619 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_SHUTDOWN); in mdfld_dsi_dpi_shut_down()
640 int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); in mdfld_dsi_dpi_set_power() local
649 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) in mdfld_dsi_dpi_set_power()
650 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
651 else if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_set_power()
652 mdfld_dsi_configure_up(dsi_encoder, pipe); in mdfld_dsi_dpi_set_power()
655 REG_WRITE(MIPI_PORT_CONTROL(pipe), in mdfld_dsi_dpi_set_power()
656 REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31)); in mdfld_dsi_dpi_set_power()
657 REG_READ(MIPI_PORT_CONTROL(pipe)); in mdfld_dsi_dpi_set_power()
659 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
660 mdfld_dsi_tpo_ic_init(dsi_config, pipe); in mdfld_dsi_dpi_set_power()
662 dev_priv->dpi_panel_on[pipe] = true; in mdfld_dsi_dpi_set_power()
664 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) in mdfld_dsi_dpi_set_power()
665 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
666 else if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_set_power()
667 mdfld_dsi_configure_down(dsi_encoder, pipe); in mdfld_dsi_dpi_set_power()
669 mdfld_dsi_dpi_shut_down(dpi_output, pipe); in mdfld_dsi_dpi_set_power()
672 REG_WRITE(MIPI_PORT_CONTROL(pipe), in mdfld_dsi_dpi_set_power()
673 REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31)); in mdfld_dsi_dpi_set_power()
674 REG_READ(MIPI_PORT_CONTROL(pipe)); in mdfld_dsi_dpi_set_power()
676 dev_priv->dpi_panel_on[pipe] = false; in mdfld_dsi_dpi_set_power()
723 static void mipi_set_properties(struct mdfld_dsi_config *dsi_config, int pipe) in mipi_set_properties() argument
727 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); in mipi_set_properties()
728 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); in mipi_set_properties()
729 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 0xffffff); in mipi_set_properties()
730 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffffff); in mipi_set_properties()
731 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14); in mipi_set_properties()
732 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xff); in mipi_set_properties()
733 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x25); in mipi_set_properties()
734 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0xf0); in mipi_set_properties()
735 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); in mipi_set_properties()
736 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); in mipi_set_properties()
737 REG_WRITE(MIPI_DBI_BW_CTRL_REG(pipe), 0x00000820); in mipi_set_properties()
738 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); in mipi_set_properties()
742 int pipe) in mdfld_mipi_set_video_timing() argument
752 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), in mdfld_mipi_set_video_timing()
754 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
756 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
758 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
760 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
762 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
764 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
766 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
770 static void mdfld_mipi_config(struct mdfld_dsi_config *dsi_config, int pipe) in mdfld_mipi_config() argument
775 if (pipe) { in mdfld_mipi_config()
783 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150A600F); in mdfld_mipi_config()
784 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), 0x0000000F); in mdfld_mipi_config()
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
789 mdfld_mipi_set_video_timing(dsi_config, pipe); in mdfld_mipi_config()
792 static void mdfld_set_pipe_timing(struct mdfld_dsi_config *dsi_config, int pipe) in mdfld_set_pipe_timing() argument
823 int pipe = mdfld_dsi_encoder_get_pipe(dsi_encoder); in mdfld_dsi_dpi_mode_set() local
828 u32 pipeconf = dev_priv->pipeconf[pipe]; in mdfld_dsi_dpi_mode_set()
829 u32 dspcntr = dev_priv->dspcntr[pipe]; in mdfld_dsi_dpi_mode_set()
832 if (pipe) { in mdfld_dsi_dpi_mode_set()
836 if (mdfld_get_panel_type(dev, pipe) == TC35876X) in mdfld_dsi_dpi_mode_set()
846 if (mdfld_get_panel_type(dev, pipe) == TC35876X) { in mdfld_dsi_dpi_mode_set()
865 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); in mdfld_dsi_dpi_mode_set()
867 mipi_set_properties(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
868 mdfld_mipi_config(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
869 mdfld_set_pipe_timing(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
881 REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000); in mdfld_dsi_dpi_mode_set()
884 REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi); in mdfld_dsi_dpi_mode_set()
886 REG_READ(MIPI_PORT_CONTROL(pipe)); in mdfld_dsi_dpi_mode_set()
888 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { in mdfld_dsi_dpi_mode_set()
890 } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { in mdfld_dsi_dpi_mode_set()
892 mdfld_dsi_dpi_controller_init(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
896 dev_priv->dpi_panel_on[pipe] = true; in mdfld_dsi_dpi_mode_set()
899 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_mode_set()
912 if (mdfld_get_panel_type(dev, pipe) == TMD_VID) { in mdfld_dsi_dpi_mode_set()
914 } else if (mdfld_get_panel_type(dev, pipe) == TC35876X) { in mdfld_dsi_dpi_mode_set()
915 mdfld_dsi_dpi_turn_on(dpi_output, pipe); in mdfld_dsi_dpi_mode_set()
918 mdfld_dsi_tpo_ic_init(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
920 mdfld_dsi_brightness_init(dsi_config, pipe); in mdfld_dsi_dpi_mode_set()
939 int pipe; in mdfld_dsi_dpi_init() local
943 pipe = dsi_connector->pipe; in mdfld_dsi_dpi_init()
945 if (mdfld_get_panel_type(dev, pipe) != TC35876X) { in mdfld_dsi_dpi_init()
950 ret = p_funcs->reset(pipe); in mdfld_dsi_dpi_init()
952 DRM_ERROR("Panel %d hard-reset failed\n", pipe); in mdfld_dsi_dpi_init()
959 p_funcs->drv_ic_init(dsi_config, pipe); in mdfld_dsi_dpi_init()
964 DRM_ERROR("Panel %d get power mode failed\n", pipe); in mdfld_dsi_dpi_init()
967 DRM_INFO("pipe %d power mode 0x%x\n", pipe, data); in mdfld_dsi_dpi_init()
978 if (dsi_connector->pipe) in mdfld_dsi_dpi_init()
984 if (mdfld_get_panel_type(dev, pipe) != TC35876X) in mdfld_dsi_dpi_init()
1005 if (dsi_connector->pipe) { in mdfld_dsi_dpi_init()